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VGA基础彩条测试实验
基于FPGA的VGA彩条测试实验,通过Verilog编写,程序通过一个key键控制几种显示模式之间的转换。。。分别有:纯色、彩条、过渡色、大方块、小方块等几种显示模式。。。因为都已在程序中设好,并没有加一些其他的模块调用。。。程序内的pll是48-40的,要用的话需根据需要更改。。分辨率有两种可供选择
- 2022-05-04 21:10:13下载
- 积分:1
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Verilog--image-sample
基于Verilog的图像采集、处理和存储程序,初学者参考,高手绕道。(Verilog-based image acquisition, processing and storage procedures, beginners reference, master bypass.)
- 2021-04-16 11:48:54下载
- 积分:1
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T13_USB
本示例为基于FPGA红色飓风一代IDS-EP1C6/12开发板的USB传输,实现了pc端接收来自FPGA开发板的数据,并显示条纹,具体使用说明见解压后的说明文档。(This example is based on red hurricane generation FPGA development board' s USB transfer IDS-EP1C6/12 realized pc client receives the data from the FPGA development board and display stripes, detailed instructions, see the documentation after decompression.)
- 2011-01-05 15:10:38下载
- 积分:1
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uart01
一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序(A RS232 computer interface implementation with FPGA-based VHDL language communications designed a very simple procedure)
- 2009-03-15 23:13:42下载
- 积分:1
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SD卡控制器verilog
sd卡读写,仿真模型,testbanch测试文件(sdcard read write and sdcard model)
- 2021-04-21 16:28:49下载
- 积分:1
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uart_slip
说明: 实现串口通讯以及SLIP协议传输数据,增加了特殊字符的转义(Realization of Serial Communication and SLIP Protocol)
- 2021-01-19 18:58:41下载
- 积分:1
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138
用vhdl 语言实现138译码器,用vhdl 语言实现138译码器,(vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl )
- 2009-04-21 12:32:17下载
- 积分:1
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RS_DesignNote
Reed-solomon decoder, encoder design note
- 2010-08-16 09:16:04下载
- 积分:1
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Continuous_delay_control_Farrow
说明: matlab代码,利用Farrow结构设计分数延时滤波器,滤波器阶数和个数可分别进行设置,利用最大最小准则近似(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)
- 2019-06-14 09:10:59下载
- 积分:1
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fifo
高速FIFO,verilog设计。速度高达130Mhz(High-speed FIFO, verilog design. Speed up to 130MHz)
- 2007-08-22 10:48:45下载
- 积分:1