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用于sopc builder添加组件用的ps/2
键盘 ipcore
用于sopc builder添加组件用的ps/2
键盘 ipcore-Sopc builder used to add components used ps/2 keyboard IPCore
- 2022-03-12 14:54:04下载
- 积分：1
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FPGA实现数字跑表
自己完成的项目，成功用vhdl语言实现数字跑表，可存储。
- 2022-05-17 20:34:58下载
- 积分：1
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source
I2C MASTER DESIGNED by Verilog
- 2020-06-18 23:40:02下载
- 积分：1
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ml505_mig_design
Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1(Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1)
- 2010-05-13 02:39:04下载
- 积分：1
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数字信号处理的FPGA实现(第4版)源码
数字信号处理的FPGA实现(第4版)的配套源码，极具参考价值。(The source code of the realization of digital signal processing on FPGA (4th edition) is of great reference value.)
- 2021-01-16 23:08:50下载
- 积分：1
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fadd16
实验用16位全加器的VHDL代码，适合初学者学习，数电学习的好工具。
(Experiment with 16-bit full adder VHDL code for beginners to learn, a good tool to learn a few power.)
- 2010-05-11 20:37:34下载
- 积分：1
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FFT_top_5
方案组成模块及系统框图
本方案设计主要由以下模块组成
1：顶层模块
2：数据输入排序模块
3：系统控制模块
4：RAM控制器模块
5：ROM控制器模块
6：蝶型单元模块(Program composition module and system diagram
The design of this scheme is mainly composed of the following modules
1: top module
2: data input sorting module
3: system control module
4:RAM controller module
5:ROM controller module
6: butterfly type unit module)
- 2017-08-23 16:23:54下载
- 积分：1
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data_swith
verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)
- 2011-07-31 23:58:17下载
- 积分：1
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5L_SVPWM_ANPC_CPLD
基于CPLD硬件描述语言编写的五电平SVPWM脉冲触发程序(Five level SVPWM pulse trigger program based on CPLD hardware description language)
- 2020-12-14 16:19:15下载
- 积分：1
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pld_Tetris
基于FPGA cyclone III EP3C16F484C6的俄罗斯方块游戏。实现双人进行，屏幕倒置，分数显示，vga接口，键盘接口等功能(Tetris game based on FPGA cyclone III EP3C16F484C6 with functions including double players, screen upside down, score, vga and keyboard interface.)
- 2020-11-06 12:39:49下载
- 积分：1
