-
使用硬件描述语言(VHDL)的实现或门
entity or1 is(a,b:in std_logic;y:out std_logic);architecture dataflow of or1 isbeginy
- 2022-03-11 13:09:15下载
- 积分：1
-
The time of the year undergraduate graduate design, signal generator and frequen...
当年本科时的毕业设计，信号发生器和频率计-The time of the year undergraduate graduate design, signal generator and frequency counter
- 2023-08-01 18:30:02下载
- 积分：1
-
AD
说明： 基于fpga的ad采样程序 可控制ad9226对信号进行采样(Ad9226 signal sampling can be controlled by ad9226 sampling program based on FPGA)
- 2020-12-19 17:09:10下载
- 积分：1
-
myuart
使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路(Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas)
- 2013-07-25 11:45:57下载
- 积分：1
-
stm32adc12路采集DMA
说明： adc采集多路采集多通道基于dma的adc采集(ADC acquisition, multi-channel acquisition and multi-channel acquisition)
- 2020-06-19 06:20:01下载
- 积分：1
-
FPGA使用Xilinx复位
Xilinx FPGA reset usage
- 2022-02-01 16:18:58下载
- 积分：1
-
spi转i2s的verilog程序，fpga是总模块，spi和i2s是子模块，shiftreg是转换...
spi转i2s的verilog程序，fpga是总模块，spi和i2s是子模块，shiftreg是转换-spi transfer i2s the verilog program, fpga is the total module, spi, and i2s is the sub-module, shiftreg is to convert
- 2022-02-13 16:18:27下载
- 积分：1
-
detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system desi...
detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.
- 2022-04-24 22:44:35下载
- 积分：1
-
vhdl经典源代码――时钟设计，入门者必须掌握
vhdl经典源代码――时钟设计，入门者必须掌握-vhdl classical source code-- Clock Design, beginners must master
- 2023-05-04 10:00:03下载
- 积分：1
-
ds312_Spartan-3E-FPGA
FPGA资料与所用元器件的数据参考手册与应用指南(ds312_Spartan-3E FPGA Family )
- 2012-09-18 21:43:54下载
- 积分：1
