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ulpi_port
ULPI UTMI conversion
- 2015-03-12 14:59:25下载
- 积分:1
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Add_sub_struc
8位加减器,八位减法器与加法器,用过一个控制端可以自由变换,采用移位加法方式,用途广泛,利用减法位补码加法的理论实现。(8 addition and subtraction, eight subtractor and adder, used a control terminal can freely change the using Shift addition, a wide range of uses, the use of subtraction complement addition theory to achieve.)
- 2012-05-14 20:36:26下载
- 积分:1
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FPGA to do VGA communication details, I am looking for a long time before starti...
FPGA做VGA通讯的详细资料,我找了很久才收集起的,很有用,可供初学者学习实用-FPGA to do VGA communication details, I am looking for a long time before starting the collection, very useful for beginners to learn practical
- 2023-03-10 18:55:03下载
- 积分:1
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vhdl代码
用vhdl语言编写的16bit的REG代码,以及iv,not and2,rca,fa,alu,acc,lfsr,mux21.
- 2023-02-03 06:35:04下载
- 积分:1
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高清电子书-Verilog HDL数字系统设计教程4本合集
说明: 高清电子书4本合集-Verilog HDL数字系统设计教程4本合集(Digital circuit design Verilog HDL digital system design)
- 2021-02-03 16:05:58下载
- 积分:1
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Arty-Z7-20-hdmi-out-master
说明: Arty Z7 20 HDMI output
- 2021-04-24 15:18:47下载
- 积分:1
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UART receiver and transmitter using vhdl
这是执行高速的代码通用异步收发器代码是用VHDL写的语言.UART是一种在传输端进行并行输入和串行输出,在接收端进行串行输入和并行输出的算法。
- 2022-02-06 12:51:51下载
- 积分:1
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用VHDL写的源代码程序,包涵三人表决器,七人表决器,全加器以及模24,模60的计数器,都是单文件的,由于程序小又多,所以集中在一起,供新学习VHDL语言的朋友...
用VHDL写的源代码程序,包涵三人表决器,七人表决器,全加器以及模24,模60的计数器,都是单文件的,由于程序小又多,所以集中在一起,供新学习VHDL语言的朋友们参考。-With VHDL source code written procedures, includes three of the voting machine, vote on seven people, and full adder, as well as modulus 24, modulus 60 counters, are single-file, as many small procedures, so together for the new Learning VHDL Language Reference friends.
- 2022-02-02 08:32:12下载
- 积分:1
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modelsim的一个非常好的教程,有程序源码,PPT,word教程
modelsim的一个非常好的教程,有程序源码,PPT,word教程-ModelSim
- 2022-03-23 03:52:36下载
- 积分:1
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it is a multiplier used in RIsc architecture based processor.......
it is a multiplier used in RIsc architecture based processor.......
- 2022-08-09 07:53:07下载
- 积分:1