-
newdecode
密码锁,大学数字eda课程顺序锁的源代码,有2位或者4位的顺序锁,可以在fpga或者cpld上实现
(Password lock, digital eda course the order of the source code of the locks, the order of two or four locks, and can be implemented on the fpga or cpld)
- 2012-03-09 00:04:57下载
- 积分:1
-
DE2_115_CAMERA
实现DE2_115开发板上配套的500万像素cmos摄像头捕捉到的画面显示在VGA上(DE2_115 development board supporting 5,000,000 pixels cmos camera to capture the screen display in VGA)
- 2020-07-09 19:08:55下载
- 积分:1
-
gold
基于vhdl语言的15位gold序列的设计的开端一部分程序(Vhdl language based on sequences of the 15 gold as part of the beginning of the design process)
- 2011-05-16 21:48:38下载
- 积分:1
-
baugh wooley codes
这是用于阵列乘法器baugh wooley 。这是写Verilog代码。它表明8位阵列乘法。这是输入含有8,8每输出有15位
- 2023-06-03 10:00:03下载
- 积分:1
-
10_ImageEdge
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)
- 2020-10-23 20:27:22下载
- 积分:1
-
多层次的中国
应用背景4联想多级cahe用Verilog。可以跑在Xilinx软件客户端模拟器。4路联想多级cahe用Verilog。可以跑在Xilinx软件客户端模拟器。4路联想多级cahe用Verilog。可以跑在Xilinx软件客户端模拟器。4路联想多级cahe用Verilog。可以跑在Xilinx软件客户端模拟器。4路联想多级cahe用Verilog。可以跑在Xilinx软件客户端模拟器。4路联想多级cahe用Verilog。可以跑在Xilinx软件客户端模拟器。关键技术你好这个代码是使用Xilinx就跑..请查看以下软件中的这一观点。
- 2022-07-12 14:19:47下载
- 积分:1
-
VHDL
A Full adder using half adder unit in vhdl
- 2010-01-05 11:39:14下载
- 积分:1
-
Modulation
产生长度为100的随机二进制序列
发送载波频率为10倍比特率,画出过采样率为100倍符号率的BPSK调制波形(前10个比特) ,及其功率谱
相干解调时假设收发频率相位相同,画出x(t) 的波形,假设低通滤波器的冲激响应为连续10个1(其余为0),或连续12个1 (其余为0) ,分别画出两种滤波器下的y(t),及判决输出(前10个比特)
接收载波频率为10.05倍比特率,初相位相同,画出x(t) 的波形,假设低通滤波器的冲激响应为连续10个1,画出两种滤波器下的y(t),及判决输出(前20个比特)
采用DPSK及延时差分相干解调,载波频率为10倍比特率,画出a, b, c, d点的波形(前10个比特)
DPSK及延时差分相干解调,载波频率为10.25倍比特率时,画出a, b, c, d点的波形(前10个比特)
DPSK及延时差分相干解调,载波频率为10.5倍比特率时,画出a, b, c, d点的波形(前10个比特)
(Produce random binary sequence of length 100
The transmission carrier frequency is 10 times the bit rate, draw a sampling rate of 100 times the symbol rate of the BPSK modulation waveform (first 10 bits), its power spectrum
Coherent demodulation of assuming the same as the phase of the transmitting and receiving frequencies, and draw the waveform x (t), assuming that the impulse response of the low pass filter 10 consecutive 1 (the remainder is 0), or 12 consecutive 1 (the remainder is 0), y (t) is drawn under the two filters respectively, and the decision output (10 bits)
The received carrier frequency is 10.05 times the bit rate, the same initial phase, draw the waveform x (t), assuming that the impulse response of the low pass filter of 10 consecutive 1, shown under two filter y (t), and decision output (20 bits)
DPSK and delay differential coherent demodulation, the carrier frequency is 10 times the bit rate, draw a, b, c, d point of the waveform (first 10 bits)
DPSK and delay)
- 2020-12-14 08:19:14下载
- 积分:1
-
T200071012217h
此源码为线性相位滤波的vhdl源码与设计心的体会,理论分分析与工程实践总结相结合,有非常大的参考价值 可直接使用。
(The source for the linear phase filter VHDL source code and design of the heart experience, theoretical analysis to summarize the combination of engineering practice, a very large reference value can be used directly.)
- 2012-07-10 16:08:08下载
- 积分:1
-
寄存器
说明: 寄存器设计文件,寄存器输入输出以及读写控制,寄存器的配置(Register design and read-write control)
- 2019-11-19 20:09:21下载
- 积分:1