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CPU
C++获取CPU占用率，一个类和一个头文件(Gets the CPU Use rate)
- 2015-01-23 11:15:32下载
- 积分：1
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CPU_Verilog
此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
- 2017-07-06 19:45:33下载
- 积分：1
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一种用于乘数的8x8的制备采用Verilog HDL语言
一个用VerilogHDL语言编写的8X8的乘法器-a Verilog HDL language used in the preparation of the multiplier 8X8
- 2023-08-11 06:05:03下载
- 积分：1
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yiweijicunq
16位右移位寄存器
下面描述的是一个位宽为16位的右移位寄存器，实际具有环形移位的功能，是在右移位寄存器的基础上将最低位的输出端接到最高位的输入端构成的。其功能为当时钟上升沿到达时，输入信号的最低位移位到最高位，其余各位依次向右移动一位。(16-bit right shift register
The following description is a right shift register with a bit width of 16 bits. It actually has the function of circular shift. It is based on the right shift register, which connects the lowest bit output terminal to the highest bit input terminal. Its function is that when the rising edge of the clock arrives, the lowest displacement of the input signal reaches the highest position, and the rest of you move one bit to the right in turn.)
- 2020-08-18 09:58:21下载
- 积分：1
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AD9777_SPI_CONFIG
verilog ad9777 ad芯片的配置程序，SPI接口协议 16bit DA(Verilog ad9777 AD chip configuration program, SPI interface protocols for 16 bit DA)
- 2020-07-29 21:08:38下载
- 积分：1
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getCPU
获取主机CPU信息，VS2008编译通过，含详细说明(Get information on the host CPU, VS2008 compiler, containing detailed instructions)
- 2014-11-27 10:07:21下载
- 积分：1
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VHDL
产生svpwm波形，可以参考下载,以便学习交流(gennerate SVPWM wave)
- 2017-11-21 15:38:29下载
- 积分：1
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UART Basic, hardwired RS232 UART.
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- 2023-05-28 14:35:03下载
- 积分：1
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xiaomi
新版 小米抢购器 -源码
已经测试，代码很有用，已经抢了好几个小米3了，希望对大家有用(The new millet to snap up- source
Have test, the code is useful, has robbed several millet 3, hope useful for everyone)
- 2014-01-08 18:26:40下载
- 积分：1
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polar_encoder_1024 (1)
该部分的主要功能是完成基于FPGA的polar码编码。(The main function of this part is to complete the FPGA-based polar code coding.)
- 2021-01-10 16:58:50下载
- 积分：1
