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阶梯波程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ladder IS
PORT(clk,reset:IN STD_LOGIC;
- 2023-07-31 13:05:03下载
- 积分：1
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v5_emac
以太网的FPGA程序实现以太网的FPGA程序实现以太网的FPGA程序实现(enternet verilog fpga)
- 2013-12-15 23:08:11下载
- 积分：1
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based-on-fpga
基于fpga的电子血压计。pdf文档，好用，内容清楚简单，转载而来(Electronic sphygmomanometer based on fpga)
- 2013-12-05 10:57:22下载
- 积分：1
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LDPC_Encoder
说明： verilog 编写的ldpc编码，含有两个文件(LDPC written by Verilog)
- 2021-03-08 19:19:28下载
- 积分：1
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Verilog-design-and-identify-book
找到这本书的完整版了。呵呵，贴出来和大家共享。这是本好书，我买了一本作为Verilog的参考书。这本书语法部分集中，便于查阅，此外讲了很多实用的设计思想。最重要的是本书薄，可以完整看完。强烈推荐。
（如果只是查阅，电子版就可以，如要完整学习，建议还是买纸质版的）(Find the full version of this book. I posted and share. This is a good book, I bought a reference book as Verilog. Syntax in this book section focuses on ease of reference, in addition to speaking a lot of useful design ideas. The most important thing is that the book is thin, you can complete reading. Highly recommended. (If you only access the electronic version to complete learning, suggestions or to buy the paper version))
- 2012-06-07 21:58:19下载
- 积分：1
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This is achieved using VHDL positive and negative pulse width modulator, the sam...
这个是用VHDL实现的正负脉宽调制器，同样是对新手有帮助，高手不必看了。-This is achieved using VHDL positive and negative pulse width modulator, the same is to help novice, you do not have to read. Ha ha
- 2022-06-19 04:51:41下载
- 积分：1
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Encryption
reversible Data Hiding in Encrypted Images by Reserving Room Before Encryption
- 2016-04-11 17:59:27下载
- 积分：1
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alu
verilog code for 8 bit alu
- 2015-06-30 18:49:10下载
- 积分：1
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TechAss-2006
un controller pi par le langage VHDL xilinx ise design 13.2
- 2013-12-16 22:53:24下载
- 积分：1
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Synchronous Resets Asynchronous Resets I am so confused! How will I ever know wh...
Synchronous Resets? Asynchronous Resets?I am so confused!How will I ever know which to use? 复位信号的论文-Synchronous Resets Asynchronous Resets I am so confused! How will I ever know which to use Minute Signal-paper
- 2022-03-02 03:52:16下载
- 积分：1
