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pl_read_write_ps_ddr
说明： PL 和 PS 的高效交互是 zynq 7000 soc 开发的重中之重，常常需要将 PL 端的大量数据实时送到 PS 端处理，或者将 PS 端处理结果实时送到 PL 端处理，但是各种协议非常麻烦，灵活性也比较差，直接通过 AXI 总线来读写 PS 端 ddr 的数据，这里面涉及到 AXI4 协议，vivado 的 FPGA 调试等。(The efficient interaction between PL and PS is the top priority of zynq 7000 SoC development. We often need to send a large amount of data from PL to PS for real-time processing, or send the processing results from PS to pl for real-time processing. In general, we will think of using DMA for processing, but various protocols are very troublesome and the flexibility is poor. This course explains how to use Axi directly Bus to read and write DDR data of PS terminal, which involves axi4 protocol, FPGA debugging of vivado, etc.)
- 2021-01-22 17:46:44下载
- 积分：1
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farrow
该程序实现多项式分数延迟（farrow）的设计。(The program polynomial fractional delay (farrow) design.)
- 2014-12-11 10:21:39下载
- 积分：1
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function-fskd
fsk在matlab上的仿真实现，一段简单的代码小程序(fsk on matlab simulation in the implementation of a simple small program code)
- 2011-06-08 21:46:15下载
- 积分：1
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FPGA design of the guiding principles, it is classic! Want to give everyone easy
FPGA设计的指导原则，很经典的！希望给大家方便-FPGA design of the guiding principles, it is classic! Want to give everyone easy
- 2023-03-11 18:40:04下载
- 积分：1
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一个简单的DDS
采用DDS方法在FPGA上实现频率发生器，最大频率设置在9999Hz，输出正弦波。
DDS是一种从相位概念出发直接合成所需要的波形的新的全数字频率合成技术。同传统的频率合成技术相比，DDS技术具有极高的频率分辨率、极快的变频速度，变频相位连续、相位噪声低，易于功能扩展和全数字化便于集成，容易实现对输出信号的多种调制等优点，满足了现代电子系统的许多要求，因此得到了迅速的发展。
- 2022-03-22 02:09:46下载
- 积分：1
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mdio
用VIVADO软件编写的，实现以太网芯片88E1510中的mdio控制模块代码，并且含有VIO仿真文件(Written in VIVADO software, the realization of the Ethernet chip 88 e1510 mdio control module of code, and contains the VIO simulation file)
- 2020-09-16 14:37:55下载
- 积分：1
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disptest
模拟示波器的现实程序，有x，y和光标。采用AD5440输出，现实效果很好。（示波器x-y方式）(Analog oscilloscope reality program, there are x, y and cursor. Using AD5440 output, real good results. (Xy oscilloscope mode))
- 2013-09-13 23:18:19下载
- 积分：1
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UART
实现了UART的底层协议，加入了控制器，其波特率可以根据使用进行调整；发送模块、接收模块相互独立，互不影响。(Realization of the underlying protocol UART, joined the controller baud rate can be adjusted according to use transmission module, receiver module are independent of each other.)
- 2013-11-30 13:25:21下载
- 积分：1
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Am29LV160D
Am29LV160D数据基本知识手册，基本原理及工作方式。(Am29LV160D Data basic knowledge Manual, the basic principle and ways of working.)
- 2013-06-05 19:26:08下载
- 积分：1
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波形发生器，带TESTBENCH，
多平台
波形发生器，带TESTBENCH，
多平台
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
-waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn
- 2023-05-18 16:15:03下载
- 积分：1
