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Altera_Audio
针对Altera的DE2/ DE1交互板的音频核心的音频编解码器（编码器/解码器），并提供了音频输入和输出的接口。(The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1
Boards and provides an interface for audio input and output.)
- 2015-04-01 22:21:49下载
- 积分：1
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uart_byte_rx
libero soc工程，实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)
- 2020-06-21 09:20:01下载
- 积分：1
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Project_Gbit
pc与fpga之间通过千兆以太网交换机实现网络通信(Network communication between PC and FPGA via Gigabit Ethernet switch)
- 2020-06-17 20:40:04下载
- 积分：1
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LVDS_SRC
实现LDVS接口数据接收 含有协议结构以及处理(lvds Verilog 512 frame)
- 2015-12-04 14:09:58下载
- 积分：1
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Four-controllable-counter
说明： 功能是（用Verilog语言的，内有比较详细的注释）：
（1）计数器的功能是从0到9999计数，并能以十进制数的形式在七段数码管上显示出来(包括七段数码管显示模块).
（2）该计数器有一个1个nclr和一个adj_plus端，在控制信号的作用下（见下表），计数器具有复位、增或减计数、暂停的功能。编写以上的程序的完整模块.
计数器的功能表
nclr adj_minus 功 能
0 0 复位为0
0 1 递增计数
1 0 递减计数
1 1 暂停计数
(Function is (with Verilog language, the more detailed comments): (1) counter function is from 0 to 9999 counts, and are able to form a decimal number on the seven-segment LED display (including the seven-segment LED display module). (2) The counter has a one nclr and a adj_plus side, under the action of the control signal (see below), the counter has reset, increase or decrease of count pause function. Complete the preparation of the above program modules. Counter function menu nclr adj_minus reset 0 0 0 0 1 1 0 counts counting suspended Count 1 1)
- 2011-03-01 22:47:51下载
- 积分：1
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project_1
说明： 基于FPGA平台的双目视觉处理项目，可以通过双目摄像头实现目标物体测距，测量大小等功能(Binocular vision processing based on FPGA platform)
- 2021-03-07 11:07:17下载
- 积分：1
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DisplayPort Link training optimization
说明： 介绍了Displayport规格中lind training的背景研究，设计和实现。(As the requirement for bandwidth continues to increase in the video market, retaining
the signal integrity becomes increasingly more difficult. For many of todays
commonly used video interfaces, there are devices that can be used to assist in this
matter. However, the use of such a device is only partially documented in the DisplayPort
specification for the receiving image device, which means that the receiving
side of the video link is free to choose its own implementation. This report presents,
together with background research and design decisions, a suggestion for such an
implementation. This implementation would need to be compatible towards a wide
range of possible video Source devices and DisplayPort cables.)
- 2021-01-11 16:48:49下载
- 积分：1
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7-segment
VHDL Design of BCD to 7-segment decoder
using PROM
- 2009-05-04 02:44:02下载
- 积分：1
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FPGA
实现温度显示，接温度传感器。在4数码管上显示小数点后两位的温度(temperture of FPGA)
- 2012-03-28 23:12:48下载
- 积分：1
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cnt60
de2开发板上的一个小程序 模60的计数器/分频器(de2 board developed a small program module 60 of the counter/divider)
- 2011-11-28 20:28:12下载
- 积分：1
