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fixpmul
verilog 有符号数 乘法器模块(verilog signed multiplyer)
- 2018-04-07 21:36:14下载
- 积分：1
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uart766
---实现的部分VHDL 程序如下。
--- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----数据帧数据由接收串行数据端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 downto 0) --- parity <= parity xor rsr(7) --- elsif std_logic_vector(length_no) = “1010” then --- rbr <= rsr --接收移位寄存器数据进入接收缓冲器--- ...... --- end if(--- achieve some VHDL procedure is as follows.--- Elsif clk1x event and then a clk1x = s--- if td_logic_vector (length_no))
- 2007-06-02 12:44:31下载
- 积分：1
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FPGA芯片亚稳态参数测试代码
资源描述在FPGA器件上测试芯片的亚稳态参数的测试方法代码
- 2022-07-04 20:54:44下载
- 积分：1
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1
verilog 典型电路设计包含各种常用电路的源码和详细的解释，适合新手使用(Verilog typical circuit design includes a variety of commonly used circuit source code and detailed explanations, suitable for beginners to use
)
- 2014-03-19 10:48:41下载
- 积分：1
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fifo
同步fifo，本设计采用同步fifo方式，中间例化ram，实现同步fifo传输
- 2022-10-13 12:40:03下载
- 积分：1
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tpc_decode_vhdl
基于VHDL的TPC译码器的设计，简述了tpc译码的算法步骤，tpc硬件实现的模块和部分vhdl程序(TPC decoder VHDL-based design, outlines the decoding algorithm steps tpc, tpc hardware modules and some vhdl program)
- 2020-11-20 10:59:37下载
- 积分：1
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mun_base
说明： adfvff f fdfs f dvdsz dz vdzsvd hdfdgvaz
- 2019-03-28 07:33:03下载
- 积分：1
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sgiarcs
ARC firmware interface defines.
- 2015-06-27 18:50:37下载
- 积分：1
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UART_RS232_Altera
在Altera开发板上实现RS232串口通信，平台为CycloneII，可通过QuartusII软件修改引脚移植到其它平台(Realize RS232 serial communication on Altera development board, platform for CycloneII, through software QuartusII modify pin portable to other platforms)
- 2016-03-25 20:29:04下载
- 积分：1
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shift example
shift example for verilog
- 2018-12-18 05:24:04下载
- 积分：1
