-
FPGA编程:基于Verilog实现的DDS波形发生器
用FPGA实现DDS波形发生器。可以实现方波,三角波,正弦波的切换,实现频率的调节。三角波和正弦波均用查表法实现。本文档包括一个主程序的代码,按键和显示的实例化程序代码、调用ROM生成的代码以及正弦波和三角波实现的数据表。
- 2022-01-26 05:31:12下载
- 积分:1
-
fsk
基于FPGA的fsk调制程序,包括载波的生成,nco的设置(FPGA-based fsk modulation procedures, including carrier generation, nco settings)
- 2016-05-12 21:00:56下载
- 积分:1
-
at7_ex04
通过LED闪烁控制器的代码,使用Vivado工具配置定义一个IP核,在用户工程中可随意添加这个IP核作为设计的一部分,如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at random in user engineering. It is as convenient to call and integrate as the IP kernel with Vivado.)
- 2018-04-09 18:41:52下载
- 积分:1
-
CRC
10G网络 CRC-32 CRC-64计算代码(10G Network CRC-32 CRC-64 Computing Code)
- 2020-06-22 19:20:01下载
- 积分:1
-
fir_vivado
此压缩包里面有基于vivado平台的工程,包括了正弦信号的产生,还有fir滤波器的设计以及fft算法的设计实现(in this package,there are three projects of
the generation of the signal of sin and the
design of fir filter and the ari)
- 2016-09-18 15:00:22下载
- 积分:1
-
sdram-control-verilog
SDRAM控制器源码,内含完整的控制器verilog源代码和测试代码,超值哈。(This readme file for the SDR SDRAM Controller includes information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.)
- 2009-12-11 15:01:46下载
- 积分:1
-
MifFileGen
VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子,生成的是一个定点的正弦数据表文件,需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)
- 2013-07-19 02:32:45下载
- 积分:1
-
XadcMicroblaze-master
用zynq实现片内的数模转换,基于最新的zynq平台(zynq xadc on FPGA arm)
- 2020-06-21 12:00:02下载
- 积分:1
-
1_Carm
经典的OV5642的verilog驱动程序(Verilog Driver of Classic OV5642)
- 2019-03-19 13:38:29下载
- 积分:1
-
imports
displayport 参考设计,可以对比自己工程做验证,另有参考设计XAPP1178未找到,采用方案为DP159 + Artix7 FPGA(xilinx displayport sink design)
- 2021-01-11 16:58:50下载
- 积分:1