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LCD_test
this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga
- 2013-07-25 14:43:43下载
- 积分:1
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w5500_spi_fpga
共两个文件,一个是对网络芯片W5500进行控制的master spi接口,另一个是w5500命令控制逻辑,命令格式按照w5500芯片的要求,分为地址段,控制段和数据段进行统一控制。此外提供w5500芯片初始化及读写控制流程图。(A total of two documents, one is the master SPI interface for network control chip W5500, the other is a w5500 command control logic, command format in accordance with the requirement of w5500 chip, divided into address segment, unified control and data segments. In addition to provide w5500 chip initialization and read and write control flow chart.)
- 2020-06-26 14:00:02下载
- 积分:1
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DW8051_ALL
包中包括,
DW8051完整的Verilog HDL代码
两本手册:
DesignWare Library DW8051 MacroCell, Datasheet
DesignWare DW8051 MacroCell Databook
三篇51论文:
基于IP 核的PSTN 短消息终端SoC 软硬件协同设计
Embedded TCP/ IP Chip Based on DW8051 Core
以8051为核的SOC中的万年历的设计 (DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!)
- 2021-05-07 09:28:36下载
- 积分:1
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Bayer2RGB
Bayer 转RGB Verilog代码实现。。5*5 窗口。在工程中应用的(Bayer to RGB Verilog code implementation. 5*5 window. Applied in Engineering)
- 2020-12-14 15:29:15下载
- 积分:1
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异步FIFO
自己编写的同步和异步FIFO的verilog代码,验证过,有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)
- 2020-07-03 07:00:02下载
- 积分:1
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FPGA控制PWM的程序
FPGA控制PWM的程序FPGA控制PWM的程序FPGA控制PWM的程序FPGA控制PWM的程序FPGA控制PWM的程序FPGA控制PWM的程序FPGA控制PWM的程序FPGA控制PWM的程序FPGA控制PWM的程序FPGA控制PWM的程序FPGA控制PWM的程序FPGA控制PWM的程序FPGA控制PWM的程序
- 2022-10-13 04:20:04下载
- 积分:1
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hls_bluebook
非常好的catapult学习书, catabult 可用于高级综合,由c产生vhdl/verilog(very nice book for catabult study)
- 2011-08-18 16:15:08下载
- 积分:1
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基于fpga的DDS程序 AD9767
基于fpga的DDS程序 可输出正弦波 方波 三角波 锯齿波(DDS program based on FPGA can output sinusoidal square wave triangular wave sawtooth wave)
- 2020-06-20 21:00:01下载
- 积分:1
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Verilog实现的gardner算法
Verilog实现的定时同步gardner算法,工程中包括整个定时环路的Verilog实现。主要模块包括:内插滤波器,定时误差检测器,环路滤波器和数字振荡控制器。同步是通信系统中的一个非常重要的内容,由于收、发端不在一起,要使它们能步调一致地协调工作,必须通过同步系统来保证。同步系统工作性能的好坏,很大程度上决定了通信系统的质量。
- 2022-08-26 01:04:55下载
- 积分:1
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RS_5_3_CODEC
完成RS(5,3)编码程序,运用Verilog语言。(Complete the RS (5,3) coding process, the use of Verilog language.)
- 2010-05-25 21:21:34下载
- 积分:1