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用verilog写的cpld的各种分频程序，希望大家指正，谢谢！
用verilog写的cpld的各种分频程序，希望大家指正，谢谢！-using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!
- 2023-01-20 06:35:04下载
- 积分：1
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印制线路板设计经验点滴
印制线路板设计经验点滴-Printed Circuit Board Design Experience
- 2022-04-09 19:37:37下载
- 积分：1
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SAR-ADC
Complete Successive approximation Analog to digital converter along with the source code
- 2013-04-21 23:42:03下载
- 积分：1
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zidong-shouhuoji
用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)
- 2014-01-05 20:42:49下载
- 积分：1
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Verilog HDL language proficiency of a good cpu code
veriloghdl语言熟练的一个很好的cpu代码
- 2022-10-31 00:00:03下载
- 积分：1
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flash_test_24
说明： 实现fpga 读写flash 在k7上验证(Realization of FPGA read-write flash verification on K7)
- 2020-06-18 20:00:02下载
- 积分：1
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用 vhdl 语言实现Rs232
Altera DE2 上使用 vhdl 语言设计 RS232 控制器。这是一个串口模块可用于嵌入系统。
- 2022-03-09 23:32:48下载
- 积分：1
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eda
EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
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- 2021-03-07 15:49:29下载
- 积分：1
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IIR-digital-filter-
采用双线性变换法设计IIR数字滤波器设计的c代码，包括低通、高通和带通(Document recording the design of IIR digital filter c code)
- 2011-09-05 17:47:58下载
- 积分：1
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vhdl代码
用vhdl语言编写的16bit的REG代码，以及iv，not and2，rca，fa，alu，acc，lfsr，mux21.
- 2023-02-03 06:35:04下载
- 积分：1
