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dds(1)
基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)
- 2017-07-11 16:36:38下载
- 积分:1
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GPS基带处理的verilog代码
GPS软件接收机基带处理的verilog程序,通过解扩解调,同步等过程将中频数据转换为原始导航数据
- 2022-03-24 13:40:54下载
- 积分:1
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伪随机led
说明: 伪随机LED灯,实现八位LED灯的随机闪烁以及其它的控制。(Pseudo-random LED lamp)
- 2020-06-21 09:40:02下载
- 积分:1
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i2c 协议
•TheI²C (使用电路) 一般被称为"两个 wireinterface"。•ThisI²C 接口将创建主设备和从设备之间的通信。•Theinterface 将读取主人的命令,并发送相应的对主人。••Ourinterface 设计包括读和写操作,将能交流掌握并通过 I2C 奴隶。
- 2022-05-14 03:46:52下载
- 积分:1
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nios2_led_one
使用nios2点亮一个led灯,使用软件quartus13.0,开发板de2-115(nios2 led quartus13.0 de2-115)
- 2013-12-11 14:32:16下载
- 积分:1
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uart2spi-master
说明: this code works with spi and uart interfaces.
- 2020-07-21 21:10:59下载
- 积分:1
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Four-controllable-counter
说明: 功能是(用Verilog语言的,内有比较详细的注释):
(1)计数器的功能是从0到9999计数,并能以十进制数的形式在七段数码管上显示出来(包括七段数码管显示模块).
(2)该计数器有一个1个nclr和一个adj_plus端,在控制信号的作用下(见下表),计数器具有复位、增或减计数、暂停的功能。编写以上的程序的完整模块.
计数器的功能表
nclr adj_minus 功 能
0 0 复位为0
0 1 递增计数
1 0 递减计数
1 1 暂停计数
(Function is (with Verilog language, the more detailed comments): (1) counter function is from 0 to 9999 counts, and are able to form a decimal number on the seven-segment LED display (including the seven-segment LED display module). (2) The counter has a one nclr and a adj_plus side, under the action of the control signal (see below), the counter has reset, increase or decrease of count pause function. Complete the preparation of the above program modules. Counter function menu nclr adj_minus reset 0 0 0 0 1 1 0 counts counting suspended Count 1 1)
- 2011-03-01 22:47:51下载
- 积分:1
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16位乘法器
基于Verilog语言的乘法器,带注释,帮助理解数字集成电路设计的乘法器实现,佩带modelsim仿真
基于Verilog语言的乘法器,带注释,帮助理解数字集成电路设计的乘法器实现,佩带modelsim仿真
- 2022-02-11 23:54:11下载
- 积分:1
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rdf0244-zc706-pcie-c-2015-4
利用FPGA开发板的PCIE接口实现数据的传输和发送。(Using the PCIE interface of FPGA development board to realize data transmission and transmission.)
- 2018-08-08 16:56:15下载
- 积分:1
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code
Due to its high modularity and carry-free addition, a redundant
binary (RB) representation can be used when designing high performance
multipliers. The conventional RB multiplier requires an additional RB partial
product (RBPP) row, because an error-correcting word (ECW) is generated
by both the radix-4 Modified Booth encoding (MBE) and the RB encoding.
This incurs in an additional RBPP accumulation stage for the MBE multiplier.
In this paper, a new RB modified partial product generator (RBMPPG) is
proposed; it removes the extra ECW and hence, it saves one RBPP
accumulation stage.
- 2017-10-01 23:34:56下载
- 积分:1