登录
首页 » VHDL » Simple ADC of signal and LED indication

Simple ADC of signal and LED indication

于 2022-01-24 发布 文件大小:4.84 kB
0 170
下载积分: 2 下载次数: 1

代码说明:

这是一个VHDL项目,用于在VIRTEX-4 xc4vsx35 FPGA板中执行接收信号的14位ADC。

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • LS165
    LS165移位寄存器的verilog语言编写(The writing of the Verilog language of LS165 shift register)
    2020-11-22 22:59:34下载
    积分:1
  • the realization of paragraph ep2c5 register verilog language, quartus 2 Simulati...
    ep2c5 实现 段寄存器 verilog语言,quartus 2 仿真-the realization of paragraph ep2c5 register verilog language, quartus 2 Simulation
    2022-03-15 03:31:41下载
    积分:1
  • FPGA
    说明:  fPGA中的竞争冒险现象的来源及其解决方法(FPGA in the source of the phenomenon of competitive risk-taking and their solutions)
    2008-12-06 17:10:46下载
    积分:1
  • 键盘输入液晶模块显示字符,在液晶显示屏上显示从PS2键盘输入的字符...
    键盘输入液晶模块显示字符,在液晶显示屏上显示从PS2键盘输入的字符-Keyboard input LCD display module characters displayed in the LCD screen from the PS2 keyboard input characters
    2022-10-02 08:20:03下载
    积分:1
  • 真正成为一个母版页,然后必须了解和使用DHTML。这里省…
    成为真正的网页制作的高手的话,必须了解并使用DHTML.这里提供了最好的手册和文档.-become truly a master pages, then have to understand and use DHTML. Here to provide the best manuals and documents.
    2023-03-13 00:40:03下载
    积分:1
  • Digital signal source, the output of different frequency, phase is the cosine si...
    数字信号源,输出不同频率,相位的正余弦信号,-Digital signal source, the output of different frequency, phase is the cosine signal,
    2022-04-23 09:40:37下载
    积分:1
  • ccd_tcp1209d-driver
    ccd驱动程序,刺程序是tcd1209的驱动程序,能够修改积分时间(ccd driver stabbed program is tcd1209 driver can modify the integration time)
    2021-02-23 09:49:40下载
    积分:1
  • car
    基于Xilinx公司的ISE软件开发的智能循迹避障小车的源代码,用Verilog语言,传感器有红外传感器以及超声波传感器(Xilinx' s ISE-based software development intelligent car tracking avoidance source code, using Verilog language, the sensor has an infrared sensor and ultrasonic sensors)
    2015-03-21 18:06:18下载
    积分:1
  • FPGA实现打车计程系统
    采用FPGA实现打车计程系统设计,实现自动计程及计费,本内容包括硬件程序设计及基于QUARTUS软件的仿真
    2022-03-25 05:53:10下载
    积分:1
  • RTC
    verilog编写的RTC(实时时钟)包含APB总线接口、时钟计时部分等(verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other)
    2009-12-19 23:51:50下载
    积分:1
  • 696518资源总数
  • 106182会员总数
  • 24今日下载