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816-1681
SPARC Assembly Language Reference
Manual
- 2014-09-20 23:42:07下载
- 积分：1
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16ChannelDeserializer
说明： LVDS De-serialization
- 2019-06-20 14:53:25下载
- 积分：1
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oc8051 Verilog代码，关于
verilog code,about oc8051
- 2023-04-16 08:45:03下载
- 积分：1
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banjian
完成一个1位全减器的设计。以全减器为元件程序完成8位减法器设计。(Completed a one minus the whole design. Full reduction is to complete eight subtraction element program design.)
- 2015-06-26 21:17:49下载
- 积分：1
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This is a verilog file which is used as a decoder
This a verilog file which is used as a decoder-This is a verilog file which is used as a decoder
- 2023-02-17 15:15:04下载
- 积分：1
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1_ADDER
说明： 第1例到第6例的源描述都是从第8例的程序包中
提取出来的,不能单独编译,这些例子的编译与
模拟请参考第8例.(Example No. 1 to the first six cases are the source described in Example 8 from the first package to extract it and can not be a separate compiler, which compiler and simulation examples please refer to the first eight cases.)
- 2008-09-09 18:00:16下载
- 积分：1
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Interfacing_RTC_with_Spartan-3_Primer_FPGA
Interfacing RTC with spartan 3
- 2013-04-04 10:13:44下载
- 积分：1
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60进制减法
相比较 代码效率高
可以进行级联
60进制减法
相比较 代码效率高
可以进行级联-60 compared to 229 subtraction efficient code can be concatenated
- 2022-01-25 18:25:04下载
- 积分：1
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FPGAsheijidaquan
说明： fpga设计常用资料大全，包含常用的FPGA程序资料，对FPGA学习者有很大的帮助。(Encyclopedia of common information fpga design, FPGA that contains commonly used procedures for information on the FPGA is very useful to learners.)
- 2009-07-25 21:45:30下载
- 积分：1
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CNT60
六十进制计数器，显示0到60.可以用数码管显示。(Six decimal counter 0-60 can use the digital display.)
- 2012-10-17 19:32:56下载
- 积分：1
