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32bit_add_exercise
32位全加器，另有一个采用流水线的版本，是基于verilog语言的，很实用，希望对大家有所帮助(32-bit full adder, while a pipelined version，code is based on verilog language, it is practical, we hope to help)
- 2016-07-19 14:31:17下载
- 积分：1
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数字波形存储器VHDL源码，基于Quartus II开发。
数字波形存储器VHDL源码，基于Quartus II开发。-Digital waveform memory VHDL source code, based on the Quartus II development.
- 2022-01-26 14:31:04下载
- 积分：1
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and VHDL source code
VHDL与源代码包-and VHDL source code
- 2022-07-21 05:42:10下载
- 积分：1
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CPU_Verilog
此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)
- 2017-07-06 19:45:33下载
- 积分：1
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基于verilog的1588V2协议的fpga实现
基于verilog的1588V2协议的fpga实现，目前项目通用代码，供大家参考(Based on verilog 1588 v2 fpga implementation of the agreement, the project general code, for your reference)
- 2021-04-26 10:58:46下载
- 积分：1
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基于FPGA的交通灯的设计 有Verilog HDL 源码、仿真图与引脚配置图，已下载实现...
基于FPGA的交通灯的设计 有Verilog HDL 源码、仿真图与引脚配置图，已下载实现
-FPGA-based design of traffic lights have Verilog HDL source code, simulation map with pin configuration map has been downloaded realize
- 2022-06-27 19:08:32下载
- 积分：1
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The use of Altera' s FPGA
使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现先进先出的队列。-The use of Altera" s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.
- 2022-05-14 03:33:12下载
- 积分：1
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FPGA programming serial communications, the entire source code. Including the si...
FPGA编程实现串口通信，源代码全。包括仿真程序。-FPGA programming serial communications, the entire source code. Including the simulation program.
- 2022-08-25 19:14:53下载
- 积分：1
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read-string-from-FLASH
read data of type character from flash memory
- 2013-09-08 03:49:15下载
- 积分：1
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本文为verilog的源代码
本文为verilog的源代码-In this paper, the source code for Verilog
- 2022-01-24 19:02:52下载
- 积分：1
