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VHDL Storage/counter design
vhdl寄存/计数器设计-VHDL Storage/counter design
- 2022-01-26 02:37:06下载
- 积分：1
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软I2C
i2c硬件程序,字节读、字节写，在modelsim6.0通过编译-the soft for i2c
- 2022-09-15 23:15:03下载
- 积分：1
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SPI 主
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- 2023-02-06 00:45:03下载
- 积分：1
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设计一个可以小时、分钟、12小时或24小时和秒的时间…
设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。
实验平台：
1. 一台PC机；
2. MAX+PLUSII10.1。
Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report
- 2022-07-22 15:10:59下载
- 积分：1
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一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (mo...
一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
- 2022-08-21 18:15:23下载
- 积分：1
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FPGA_Timing_Constraints_byCamp
简要地说明时序约束的内容，对入门级的朋友相当起到引导的作用(Briefly describes the content of timing constraints on entry-level friends rather play a guiding role)
- 2013-10-30 23:20:53下载
- 积分：1
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SHIFT_8REG是8位的一个具有移位功能的寄存器，每一次数据打入都会从这个寄存器的最低位打入，并相应进行向左移位。
ODD_110BREG是一个3位的备...
SHIFT_8REG是8位的一个具有移位功能的寄存器，每一次数据打入都会从这个寄存器的最低位打入，并相应进行向左移位。
ODD_110BREG是一个3位的备份寄存器，寄存器中存放的是奇数帧的同步头，也就是110。
EVEN_9BHREG是一个8位的备份寄存器，寄存器中存放的是偶数帧的同步头，也就是10011011。这两个寄存器的初始值在系统一开始就打入。
-SHIFT_8REG is eight with a displacement of the functional Register, Each will enter the data from the register into the lowest point, and the left shift accordingly. ODD_110BREG is a three backup Register, the Register is stored in the odd frame synchronization head, is 110. EVEN_9BHREG 8 is a backup Register, which register is kept even the first frame synchronization, is 10011011. This register the two initial value of the system into a start.
- 2022-05-15 03:11:22下载
- 积分：1
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跑马灯led_horse vhdl cpldfpga
跑马灯led_horse vhdl cpldfpga-led_horse vhdl cpldfpga
- 2022-12-03 00:40:03下载
- 积分：1
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murata ads 2011 model
ADS是安捷伦科技公司的EDA软件这个库的等效电路数据使用ADS2011，后来只。（请参阅ADS2009U1有关图书馆的信息和更早版本）
- 2023-09-10 01:30:04下载
- 积分：1
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MemoryGame-master
在开发板EGO1上实现的图形记忆游戏，白块按下确认建，黑色块不按确认键(memory game in verilog)
- 2020-12-19 16:29:10下载
- 积分：1
