-
鸟哥的Linux私房菜——基础学习篇(第四版)
全面了解Linux系统,构建服务器,用Vim写写程序(Fully understand the Linux system, build the server, write programs with Vim.)
- 2018-11-02 10:56:59下载
- 积分:1
-
Verilog计数器、编码器、加法器
verilog编码器、计数器、加法器的程序(Verilog encoder, counter, adder procedures)
- 2019-01-26 21:50:01下载
- 积分:1
-
一个交通灯的vhdl语言实现 用 VC的 1.在指定的文件夹内查找某个文件 2.获取系统文件夹的路径, 要求显示windows system tem...
一个交通灯的vhdl语言实现 用 VC的 1.在指定的文件夹内查找某个文件 2.获取系统文件夹的路径, 要求显示windows system temp 当前目录的路径 C语言 跳马问题:在5*5的棋盘上,以编号为1的点出发,按日只跳马,要求不重复地跳所有位置,求出符合规则所有跳马的方案 1 6 15 10 21 14 9 20 5 16 19 2 7 22 11 8 13 24 17 4 25 18 3 12 23 -a traffic light VHDL language of a VC. The designated folders to search within a document 2. Access to the system folder path, requested that the current windows system temp directory path C language vault : 5* 5 in the chessboard to the No. 1 starting point, the only daily vault and asked not to repeat all locations to jump to get in line with all rules of the program vault 1 6 15 10 21 14 9 20 5 16 19 2 7 22 11 8 13 24 17 4 25 18 3 12 23
- 2022-02-14 11:48:06下载
- 积分:1
-
iq_balance
调整iq幅度不平衡的模块,可以解决载漏和边带问题。(Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.)
- 2021-04-23 17:48:47下载
- 积分:1
-
Regs
一个小寄存器堆,使用参数化编程,附有仿真代码,可直接在vivado(2018.2版本及以后)上运行(A small register heap, using parametric programming)
- 2019-04-03 14:19:55下载
- 积分:1
-
USB1.1 IP核心控制设备,用硬件描述语言…
usb1.1的设备控制器IP核,是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.
- 2022-01-30 21:54:55下载
- 积分:1
-
this project is based on half adder ,full adder,half subtractor and full subtrac...
this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural techniques are used.
-
this project is based on half adder ,full adder,half subtractor and full subtractor using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural techniques are used.
- 2022-12-30 21:40:03下载
- 积分:1
-
用vlog语言编制程序CPU控制器源代码…
用vlog语言编写的cpu控制器源代码,用于fpga的硬件编程实验-vlog language used in the preparation of cpu controller source code for programming fpga hardware experiments
- 2022-02-15 12:37:59下载
- 积分:1
-
~ VHDL源代码的FFT IP核
FFT变换的IP核的源代码 VHDL~-FFT IP core of the source code for VHDL ~
- 2022-02-25 23:54:48下载
- 积分:1
-
test
利用ANSYS有限元仿真软件对复合材料进行异常检测仿真实验,程序为一损伤样板模型(ANSYS finite element simulation software for composites simulation anomaly detection, the program is a damage model model)
- 2016-04-04 11:15:04下载
- 积分:1