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This tutorial presents an introduction to Altera’s Nios R
II processor, which...
This tutorial presents an introduction to Altera’s Nios R
II processor, which is a soft processor that can be in-
stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor and its associated memory and peripheral components are easily instantiated by using Altera’s SOPCBuilder in conjuction with the Quartus R II software.
- 2023-06-21 11:25:02下载
- 积分：1
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由VHDL 语言实现的D触发器利用的是QUARTUES环境已经得到验证
由VHDL 语言实现的D触发器利用的是QUARTUES环境已经得到验证-By the VHDL language using the D flip-flop is QUARTUES environment has been tested
- 2022-05-08 21:19:33下载
- 积分：1
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dp_xiliux the CPLD Verilog design experiments, clock demo. code test.
dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, clock demo. code test.
- 2022-12-25 17:55:03下载
- 积分：1
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LED
按键控制数码管显示，从0到9显示，八位数码管(Button control digital tube display)
- 2017-11-13 20:19:42下载
- 积分：1
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VHDL源代码包
VHDL源代码包-VHDL source code
- 2022-05-22 07:07:38下载
- 积分：1
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FPGA_four_num_code_lock
说明： 基于EasyFPGA030的四位数字密码锁。(Based on the four-digit lock EasyFPGA030.)
- 2010-04-29 15:16:29下载
- 积分：1
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dianzhen
基于FPGA的16*16点阵中文LED显示，另带有几个简单的中文汉字的点阵数据。(FPGA-based 16* 16 dot matrix Chinese LED display, and the other with a few simple lattice data Chinese characters.)
- 2014-05-30 21:47:37下载
- 积分：1
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ANALYSIS-OF-ALL-GATES
ANALYSIS OF ALL GATESS
- 2013-11-12 13:33:55下载
- 积分：1
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jishi
计时器=================(Timer =================)
- 2009-12-27 21:41:10下载
- 积分：1
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VerilogHDL课件，老师现在正拿这个上课
VerilogHDL课件，老师现在正拿这个上课-VerilogHDL courseware, teachers are now using this class
- 2022-05-25 16:25:07下载
- 积分：1
