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costas
costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块(costas the verilog program, including multipliers, DDS, phase detector, loop filter modules)
- 2011-08-19 10:20:53下载
- 积分：1
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上海外滩看到的最大的LED显示屏的内核源代码，主要是完成视频信号的远距离传输的编解码与接口转换...
上海外滩看到的最大的LED显示屏的内核源代码，主要是完成视频信号的远距离传输的编解码与接口转换-Shanghai Bund to see the largest LED display in the kernel source code, mainly to complete the long-distance video signal transmission codec conversion and interface
- 2022-01-25 18:54:47下载
- 积分：1
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Verilog代码转换到AHB总线APB
verilog code for apb to ahb convert
- 2023-04-27 12:35:03下载
- 积分：1
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verilog编写的状态机检测00100序列.
实现 input:...011000010010000...
output:...0000000001...
verilog编写的状态机检测00100序列.
实现 input:...011000010010000...
output:...000000000100100...
并且 用测试模块来验证状态是否正确工作-verilog prepared by the state machine detected 00,100 sequences. Achieve input : ... ... 011000010010000 output : 000000000100100 ... ... and test module used to verify the state is working
- 2022-06-16 14:06:28下载
- 积分：1
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cpu_design
FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告(FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language)
- 2020-12-03 13:09:25下载
- 积分：1
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24小时计时时钟
实现24小时计时，因为位数不够，这里是12进位，可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分：1
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DES
说明： 自己写的DES的verilog实现。输入输出实现了并转串。(DES algorithm implemented in verilog.)
- 2020-12-03 16:19:25下载
- 积分：1
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50846288C
verilog 硬件编程实现bpsk调制(verilog hardware, programming bpsk Modulation)
- 2009-10-29 20:20:33下载
- 积分：1
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verilog HDL编写的出租车计费系统
verilog HDL编写的出租车计费系统-verilog HDL prepared Taxi Accounting System
- 2022-05-06 06:53:34下载
- 积分：1
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fifo
说明： FPGA的fifo与dsp的emif接口测试程序(EMIF interface test program for FIFO and DSP of FPGA)
- 2020-12-03 16:59:25下载
- 积分：1
