网站首页

登录

AES加密算法verilog源码

于 2023-05-16 发布文件大小:1.79 MB

 0  213

下载积分: 2 下载次数: 1

我要下载

代码说明：

AES加密算法verilog源码 This project is the hardware implementation of the Advanced Encryption Standard with a key size of 128 bits. The implementation adheres to the FIPS-197 document which explains the same.The core can do both encryption as well as decryption.The documents aes_arch.doc and aes_tb_readme.txt give further details of the rtl implementation and test bench respectively. This code was written originally with 128 bit ports for both input and key but later converted to 64 bits each to save on i/o pins. It can be reverted back easily if one just changes the port widths and dispenses with the load signal in the top module and making approriate changes in process where load is used.Synthesis results have been included for Xilinx Spartan-3 device.The directory structure of the project is as under- AES128

下载说明：请别用迅雷下载，失败请重下，重下不扣分！

发表评论

0 个回复

AHB 仲裁
仲裁者 AHB 泛型代码。与任何 AHB 设计的工作。它将支持两个拆分和重试交易以及。它将支持达 9 大师，它可以通过改变参数值在测试工作台中的改变了。它叉骨界面 also.one 可以连接此代码到任何协议通过改变议定书》的要求。

2022-02-02 12:21:13下载

积分：1
FM
说明：基于FPGA和弦！！！音乐芯片的设计与实现！！！(Design and implementation of FPGA chip based on the chord music)

2015-01-07 17:02:29下载

积分：1
pro1
对用开发板上开关产生的信息做汉明编码并通过串口发送至电脑(The Hamming code is generated from the switch on the development board and sent to the computer through the serial port.)

2018-11-15 17:01:21下载

积分：1
tPad_Camera
tPad DE2-115/70开发板可用的摄像头采集、显示程序，QT10.0以上环境可用，原装代码，可以进行修改加以使用，如使用到倒车影像系统中，视频显示等。(tPad DE2-115/70 development board available cameras capture, display program, QT10.0 over the environment is available, the original code can be modified to be used, such as the use of the reversing video system, the video display.)

2020-07-09 19:58:55下载

积分：1
RISC-V-Reader-Chinese-v2p1
说明： RISC-V 芯片设计规范,很有参考价值，开源芯片设计必备参考资料，希望对大家有帮助。(The RISC-V Foundation is chartered to standardize and promote the open RISC-V instruction set architecture)

2020-07-01 23:00:02下载

积分：1
msp430x41x
低电源电压范围为1.8 V至3.6 V 超低功耗： - 主动模式：280μA，在1 MHz，2.2伏 - 待机模式：1.1μA - 关闭模式（RAM保持）：0.1μA 五省电模式欠待机模式唤醒超过6微秒 16位RISC架构， 125 ns指令周期时间 12位A/ D转换器具有内部参考，采样和保持，并 AutoScan功能 16位Timer_B随着三† 或七‡ 捕捉/比较随着阴影寄存器具有三个16位定时器A 捕捉/比较寄存器片上比较器串行通信接口（USART），选择异步UART或同步SPI软件： - 两个USART（USART0 USART1）的† - 一个USART（USART0）‡ 掉电检测电源电压监控器/监视器可编程电平检测串行板载编程，无需外部编程电压安全可编程代码保护融合(Low Supply-Voltage Range, 1.8 V to 3.6 V Ultralow-Power Consumption: − Active Mode: 280 µ A at 1 MHz, 2.2 V − Standby Mode: 1.1 µ A − Off Mode (RAM Retention): 0.1 µ A Five Power Saving Modes Wake-Up From Standby Mode in Less Than 6 µ s 16-Bit RISC Architecture, 125-ns Instruction Cycle Time 12-Bit A/D Converter With Internal Reference, Sample-and-Hold and Autoscan Feature 16-Bit Timer_B With Three† or Seven‡ Capture/Compare-With-Shadow Registers 16-Bit Timer_A With Three Capture/Compare Registers On-Chip Comparator Serial Communication Interface (USART), Select Asynchronous UART or Synchronous SPI by Software: − Two USARTs (USART0, USART1)† − One USART (USART0)‡ Brownout Detector Supply Voltage Supervisor/Monitor With Programmable Level Detection Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse)

2012-05-31 15:26:33下载

积分：1
shuzijishiqi
基于VHDL的数字计时器，手动可控正计时和倒计时(含复位键和使能键)(VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key))

2016-12-05 19:57:07下载

积分：1
adda
基于FPGA 黑金ALINX 515的 ADDA采样模块源码（需调试）(ADDA Sampling Module Source Code Based on FPGA Heijin ALINX 515)

2020-06-20 13:00:01下载

积分：1
给予内部晶振对外部时间码校正模块
对于不同竞争可能出现的偏差，采用修改计数方式对多个设备时间码进行修正，时最后输出时间码时同步的，精度可以达到10的付8次方

2022-01-26 05:02:59下载

积分：1
vga
说明：实现在屏幕上显示绿色和红色相间的水平条纹。其中，vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)

2020-06-24 02:00:02下载

积分：1

696518资源总数
106208会员总数
21今日下载