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0702
七段数码管显示数字时 使用VHDL语言编写(VHDL The seven-segment LED display digital clock)
- 2013-03-25 22:31:09下载
- 积分：1
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Desktop
qpsk的fpga实现，包含调制和解调部分，使用verilog语言(FPGA implementation of QPSK)
- 2019-03-16 02:52:26下载
- 积分：1
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Archive
TASKS OF TWO TYPES CAN BE RUN FOR EVERY 2 MIN.
- 2012-11-14 15:12:43下载
- 积分：1
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This code for countor . it is design in verilog HDL.
This code for countor . it is design in verilog HDL.
- 2022-07-27 18:33:04下载
- 积分：1
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hssdrc IP核的可配置的通用SDRAM控制器的自适应银行…
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is licensed under MIT License
- 2022-09-20 22:10:03下载
- 积分：1
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全部通过，是我的精心设计，完全满足初学者的要求。
全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
- 2022-02-20 15:52:11下载
- 积分：1
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matlab程序
说明： OFDM信号的发送与接收 ，需要自取。时域图，模糊图，削峰。(Sending and receiving of OFDM signal)
- 2020-12-17 12:56:10下载
- 积分：1
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用于sopc builder添加组件用的ps/2
键盘 ipcore
用于sopc builder添加组件用的ps/2
键盘 ipcore-Sopc builder used to add components used ps/2 keyboard IPCore
- 2022-03-12 14:54:04下载
- 积分：1
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FFT_top_5
方案组成模块及系统框图
本方案设计主要由以下模块组成
1：顶层模块
2：数据输入排序模块
3：系统控制模块
4：RAM控制器模块
5：ROM控制器模块
6：蝶型单元模块(Program composition module and system diagram
The design of this scheme is mainly composed of the following modules
1: top module
2: data input sorting module
3: system control module
4:RAM controller module
5:ROM controller module
6: butterfly type unit module)
- 2017-08-23 16:23:54下载
- 积分：1
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canny_edge_detector_latest2
very good code for edge detection based on vhdl programming.
- 2021-04-14 13:08:55下载
- 积分：1
