登录
首页 » Verilog » guardar 纪念馆 en 显示德 7 segmentos con 宝通德重置语言

guardar 纪念馆 en 显示德 7 segmentos con 宝通德重置语言

于 2023-05-29 发布 文件大小:174.50 kB
0 117
下载积分: 2 下载次数: 1

代码说明:

电路在语言中建模与入席,保存和显示数据与一个重置按钮 7 分割。

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • irig_b
    用来实现IRIG_B码的解码程序,在XILINX ISE上运行过没有问题,(Used to achieve IRIG_B code decoding process, in XILINX ISE run-off is no problem,)
    2021-04-06 14:49:03下载
    积分:1
  • IEEE Standard for Verilog 2005
    IEEE Standard for Verilog 2005
    2017-06-05 13:53:12下载
    积分:1
  • DDC
    verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用,好用。(Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.)
    2009-03-23 20:42:56下载
    积分:1
  • 016_versat_updown_counter
    说明:  Verilog实现的加减法功能计数器,通过独立的自增自减信号控制计数器进行自增计数和自减计数(Function counter of addition and subtraction implemented by Verilog)
    2019-11-27 23:16:27下载
    积分:1
  • labview-filter
    数字滤波器包含IIR数字滤波器和FIR数字滤波器。本设计的工作主要是Labview软件部分,包括信号生成模块、滤波模块、显示模块的设计(IIR digital filter comprises a digital filter and FIR digital filters. The design work is mainly Labview software parts, including signal generation module, filter module, display module design)
    2014-06-05 22:22:37下载
    积分:1
  • DW8051_ALL
    包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 (DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!)
    2021-05-07 09:28:36下载
    积分:1
  • ProtelDesignInVHDL
    说明:  Protel中VHDL设计参考,pdf,不错的一本学习VHDL的书(Protel design in VHDL)
    2009-08-21 11:16:24下载
    积分:1
  • ATSHA204_SHA256HMAC
    ATSHA204_S加密芯片资料,学习使用该芯片必读资料(ATSHA204_S encryption chip data, required reading for learning to use the chip)
    2013-09-22 10:34:43下载
    积分:1
  • complex_timing_by_Primetime
    用PrimeTime的技巧,解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)
    2012-08-05 19:07:47下载
    积分:1
  • xge_mac_latest.tar
    用Verilog编写的以太网控制器,可以使用,里面是全部verilog源码(Ethernet controller based on Verilog, can be used directly, all verilog files)
    2015-12-21 17:12:51下载
    积分:1
  • 696518资源总数
  • 105918会员总数
  • 20今日下载