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automachine
自动售货机的状态机实现
自动售货机的状态机实现(this is a automachine)
- 2011-07-06 13:40:28下载
- 积分:1
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chuzuche
出租车vhdl程序,并带有testbench仿真程序,通过开始按键复位,然后根据行使信号进行公里计数,起步价3公里8元钱,超过3公里一公里1元钱(Taxi vhdl program, with a testbench simulation program, started by the reset button, then the exercise kilometer count signal, starting at 3 km 8 yuan, more than three kilometers one kilometer dollar.)
- 2016-07-14 14:41:24下载
- 积分:1
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3*3按键控制流水灯
verilog HDL语言程序,运行后3*3矩阵键盘按键控制实验板led依次点亮,达到流水灯的效 果
- 2022-10-19 20:20:04下载
- 积分:1
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HW2+李东方+2019211409
说明: 基于数据通路和控制器的高校简单PPM设计(PPM design based on datapath and controller)
- 2020-11-25 02:19:32下载
- 积分:1
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VHDLdevelopment-court
vhdl数字电路设计经典教程,入门必备,非扫描版,非常清晰(vhdl digital circuit design classic handbook, entry-essential, non-scan version, very clear)
- 2011-07-13 16:23:18下载
- 积分:1
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29_ad9226_test
本实验将采用双通道 12bit AD 9226在开发板上实现数据采集和模数
转换的功能(This experiment will use dual channel 12bit AD 9226 to realize data acquisition and module on the development board.
The function of conversion)
- 2020-12-06 21:09:21下载
- 积分:1
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EEPROM_RD_WR
本程序包含:EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块(eeprom_wr.v)、信号产生模块(signal.v)和顶层模块(top.v) ,这样可以有一个完整的EEPROM的控制模块和测试文件,本文件通过测试。(This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (eeprom_wr.v), signal generator module (signal.v) and top-level module (top.v), this can have a EEPROM complete control module and test document, this document is to pass the test.)
- 2008-12-23 15:04:20下载
- 积分:1
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UART Verilog sorce 代码和仿真代码和 FIFO 代码
它由 verilog 语言编程和主要代码是 UART,主要来源代码是 uart_receiver.v /uart_transmitter.v/lpm_mux0.v/myfifo.v......一些波形文件可以帮助您了解更多的模拟信息。
- 2022-03-24 03:32:08下载
- 积分:1
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dpll
用verilog编写的全数字锁相环,包括鉴相器,模K计数器,加减脉冲模块和分频模块,都经过验证(verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider )
- 2014-04-22 08:36:53下载
- 积分:1
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Cordic实现Sin Cos, Verilog
verilog语言实现的cordic算法,计算sin cos三角函数
- 2023-06-11 16:25:04下载
- 积分:1