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VHDL language is designed to be simple to use the CPU, the focus of the design o...
用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the final design of the micro-operation microinstruction to verify the correctness of the design. Can achieve the basic add, subtract, multiply, divide, transfer, recycling and other operations.
- 2022-01-26 04:06:25下载
- 积分：1
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verilogdct
dct实现verilog hdl的数字图像处理，源代码(dct achieve verilog hdl digital image processing, source code)
- 2020-12-02 17:49:26下载
- 积分：1
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walsh
沃尔什函数发生器工程文件，Quartus Ⅱ 13.0版本(Walsh Function Generator)
- 2020-07-03 08:20:01下载
- 积分：1
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adc
采用quartus的数模转换模块，RTL电路图(DAC module, RTL circuit diagram)
- 2018-08-27 11:09:01下载
- 积分：1
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rdf0244-zc706-pcie-c-2015-4
利用FPGA开发板的PCIE接口实现数据的传输和发送。(Using the PCIE interface of FPGA development board to realize data transmission and transmission.)
- 2018-08-08 16:56:15下载
- 积分：1
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counter2
spartan-3e fpga vhdl 实现的计数器 记满后点亮小灯(spartan-3e fpga vhdl counter to light led)
- 2012-04-23 16:38:30下载
- 积分：1
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DPLL
基于VHDL语言的DPLL电路的设计，给出了设计方案和部分源代码
(DPLL)
- 2010-05-11 19:34:11下载
- 积分：1
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Altera-FPGA-sigmoid
利用quartus II 软件采用verilog语言设计了一个sigmoid激活函数(this work is a sigmoid ,use verilog language)
- 2018-11-22 15:31:29下载
- 积分：1
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VHDL语言基本数学运算库
VHDL语言基本数学运算库-VHDL basic arithmetic library
- 2022-03-03 06:03:30下载
- 积分：1
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adder16b
说明： 潘松那本书上用vhdl语言描述的16位并入并处加法器(Pan book vhdl language used to describe the 16-bit adder into his)
- 2009-07-23 17:02:22下载
- 积分：1
