本系统参照片上系统的设计架构、采用FPGA与SPCE061A相结合的方法，以SPCE061A单片机为进程控制和任务调度核心；FPGA做为外围扩展，内部自建系统总...

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本系统参照片上系统的设计架构、采用FPGA与SPCE061A相结合的方法，以SPCE061A单片机为进程控制和任务调度核心；FPGA做为外围扩展，内部自建系统总线，地址译码采用全译码方式。FPGA内部建有DDS控制器，单片机通过系统总线向规定的存储单元中送入正弦表；然后DDS控制器以设定的频率，自动循环扫描，生成高精度，高稳定的5Hz基准测量信号。-The system with reference to the design of system-on-chip architecture, used a combination of FPGA and SPCE061A approach to SPCE061A Singlechip for process control and scheduling core mission FPGA for external expansion, internal self-system bus, address decoding using the entire translated code approach. DDS has built internal FPGA controller, microcontroller through the system bus to the provisions of the storage unit into the sine table DDS controller and then to set the frequency, automatic cycle of scanning, to generate high precision and high stability of the baseline measurement 5Hz signal.