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sopc_test
在altera公司FPGA上自己构建了一个最简单的niosii sopc系统(Altera FPGA company on its own to build a simple system niosii sopc)
- 2014-04-30 10:24:55下载
- 积分：1
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dpwm_8bit
数字脉冲宽度调制，将输入的数字信号转换为对应占空比的模拟波形(Digital pulse width modulation, the digital signal is converted to the corresponding input of the duty cycle of the analog waveform)
- 2020-06-28 16:00:02下载
- 积分：1
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A basic SDH transmission module STM
一个SDH中最基本传输模块STM-1的帧头检测器，verilog编程实现-A basic SDH transmission module STM-1 Header detector, verilog Programming
- 2022-02-07 03:42:51下载
- 积分：1
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vhdl_codes
D-flip flop vhdl implement code
- 2012-04-13 14:03:13下载
- 积分：1
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TS_CHANNEL_656
利用ITU656接口传输数据流的方法!已得到应用!(ITU656 interface transfer data streams using the method! Has been applied!)
- 2010-02-23 14:16:18下载
- 积分：1
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Input from the MIC for some audio and then AOUT interface from broadcast in the...
从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code
- 2023-06-09 21:15:03下载
- 积分：1
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Rs232_Trans
controller for sending serial data at different speeds
- 2009-04-28 02:41:14下载
- 积分：1
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lic_Xilinx_ISE_Vivado
这是Xilinx ISE 14.X以及vivado、vivado_hls的license，亲测可用(Xilinx ISE 14.x vivado, vivado_hls license, pro-test available)
- 2013-04-26 14:51:09下载
- 积分：1
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3。这个核心的分配必须是免费的。充电
3. Distribution of this core must be free of charge. Charging is -- allowed only for value added services. Value added services -- would include copying fees, modifications, customizations, and -- inclusion in other products.-3. Distribution of this core must be free of charge. Charging is-- allowed only for value added services. Value added services-- would include copying fees, modifications, customizations, and-- inclusion in other products.
- 2022-01-31 13:42:46下载
- 积分：1
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ddr3_model
一个verilog语言开发编写的简单的ddr3模型(A simple model ddr3, written with verilog language)
- 2020-08-26 17:38:13下载
- 积分：1
