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verilog 232串口收发程序 在开发板上测试成功过
verilog 232串口收发程序 在开发板上测试成功过-verilog 232 serial port transceiver program already had some success in the development of on-board test ^ ^
- 2022-02-11 11:33:57下载
- 积分:1
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P4 (3)
支持{addu、subu、lui、ori、jal、jr、lw、sw、nop}指令集的单周期CPU,verilog硬件描述语言实现(Support {addu, subu, lui, ori, jal, jr, lw, sw, nop} instruction set of one-cycle CPU, Verilog hardware description language implementation)
- 2018-12-02 17:22:40下载
- 积分:1
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这是“VHDL设计”讲稿,希望对初学者有用,
这是“VHDL设计”讲稿,希望对初学者有用,-"VHDL design" script, useful for beginners, thank you! !
- 2022-03-13 04:27:24下载
- 积分:1
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奇数奇偶校验器使用VHDL的有限状态机
An odd parity checker as an FSM using VHDL
- 2022-02-24 23:42:29下载
- 积分:1
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State machine used to achieve code lock
用状态机实现密码锁State machine used to achieve code lock-State machine used to achieve code lock
- 2022-10-12 19:25:03下载
- 积分:1
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Baseband_line_code
基于VHDL语言的基带线路码产生电路设计(毕业论文),内涵完整的源代码(Based on VHDL language baseband line code generation circuit design (Thesis), meaning the complete source code)
- 2010-07-03 22:38:09下载
- 积分:1
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Риторика_Зачетная работа
说明: access must be conf urr arr
- 2019-05-29 20:23:53下载
- 积分:1
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091655
基于fpga的coms摄像头
扫描,参考文献,(Fpga based on the coms camera scan, reference literature,)
- 2010-08-09 01:03:12下载
- 积分:1
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traffic 2
说明: 实现主干道交通灯显示,以状态机程序实现,并用数码管进行红绿灯倒计时的显示,内置计数模块,交通灯控制模块,数码管显示模块,并对各模块用电路图的方式进行连接。对于学习VHDL语言有所帮助。(The main road traffic light display is realized by the state machine program, and the digital tube is used to display the traffic light countdown. The counting module, the traffic light control module and the digital tube display module are built in, and each module is connected by the circuit diagram. It is helpful for learning VHDL.)
- 2020-06-25 19:55:12下载
- 积分:1
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LS165
LS165移位寄存器的verilog语言编写(The writing of the Verilog language of LS165 shift register)
- 2020-11-22 22:59:34下载
- 积分:1