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FSM
It is the FSM implemented in Xylinx 14.7 on FPGA
- 2015-09-28 15:50:09下载
- 积分:1
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两个加法器和乘法器与并行处理的使用…
利用两个加法器和两个乘法器一起并行处理来实现
- 2022-05-28 05:02:29下载
- 积分:1
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BoneMicoren
Bone microphnoe simulator.
this is a trial to de-noise the bone microphone signals.
This also utilizes om-lsa algorithm
- 2012-12-12 04:47:28下载
- 积分:1
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基于FPGA的数字频率计VHDL源码(精确到1.1hz至20.0mhz)
当时是用于课程设计而编写的代码,经过的运行没有错误。精确率很高。基于FPGA的数字频率计VHDL源码(精确到1.1hz至20.0mhz)
- 2022-02-14 20:48:42下载
- 积分:1
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双电梯控制器
说明: 使用verilog实现的双电梯控制器,1-9层,仿真通过(a bi-elevator controller written in VerilgHDL, which has floor1-9, simulation passed)
- 2020-06-17 11:44:27下载
- 积分:1
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dft
verilog语言实在点变换DFT源代码,可以配合软核或者其他CPU进行综合FFT变换,也可以单独使用生成module!(verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!)
- 2009-05-09 14:29:47下载
- 积分:1
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gtwizard_254_127_ex_1113_3
说明: 配置GTH ip的例子工程,选用7 series 芯片的GTH 113quad的四个通道,在程序中每个链路利用自己的恢复时钟进行数据解码,所以四个通道可以各自独立运行;成功工作在2.54Gb/s的链路状态,长时间(>24小时)的测试,误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)
- 2019-06-17 21:33:56下载
- 积分:1
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四位静态数码管控制器,含详细的中文注释,VERILOT源码....
四位静态数码管控制器,含详细的中文注释,VERILOT源码.-4 static digital tube controller, with detailed notes in Chinese, VERILOT source.
- 2022-03-29 22:12:43下载
- 积分:1
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AD9767_DDS
说明: 基于fpga的DDS程序 可输出正弦波 方波 三角波 锯齿波(DDS program based on FPGA can output sinusoidal square wave triangular wave sawtooth wave)
- 2020-06-20 21:00:01下载
- 积分:1
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20190718
uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device
- 2020-06-21 21:40:01下载
- 积分:1