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RISC
说明： RISC全部源码，包含仿真文件，使用makefile脚本编写，能通过vcs编译(RISC all source code, including simulation files, using makefile script, can be compiled through VCS)
- 2020-04-14 22:10:52下载
- 积分：1
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LIP2242CORE_otp_rom
Verilog OTP ROM source code
- 2011-01-31 09:54:45下载
- 积分：1
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hdb3a
快速实现HDB3码与普通码二进制码的转换，方便学习与了解HDB3码的转换(Quickly achieve HDB3 code and common code binary code conversion, facilitate learning and understanding HDB3 code conversion)
- 2020-11-09 15:09:48下载
- 积分：1
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VerilogHDL
基于verilog convolutional coding
的卷积编码(verilog convolutional coding
)
- 2012-05-09 22:56:42下载
- 积分：1
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multi16
有符号16位乘法器。经典booth编码。拓扑结构为wallance树。加法器类型是进位选择加法器。(Number system: 2 s complement
Multiplicand length: 16
Multiplier length: 16
Partial product generation: PPG with Radix-4 modified Booth recoding
Partial product accumulation: Wallace tree
Final stage addition: Carry select adder
)
- 2013-01-01 14:13:58下载
- 积分：1
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sd_slave_device
verilog source code for SD card SLAVE DEVICE IP-Core
- 2021-04-12 22:18:56下载
- 积分：1
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verilog实现的积分梳状滤波器
采用verilog实现的三级CIC抽取器，输入8位数据，输出26位数据，使用有限状态机用于实现下采样，包括积分器实现模块和梳状器实现模块
- 2022-02-20 13:58:22下载
- 积分：1
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中值滤波verilog
中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog中值滤波verilog
- 2023-03-28 00:30:04下载
- 积分：1
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jt2
基于FPGA的交通灯代码，VHDL语言书写。适合新手学习vhdl语言时使用(FPGA-based traffic light code, VHDL language writing. Suitable for novice learning vhdl language used when)
- 2013-10-26 13:30:26下载
- 积分：1
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Advanced-FPGA-Design
Advanced FPGA Design - Architecture, Implementation, and Optimization(Advanced FPGA Design- Architecture, Implementation, and Optimization)
- 2015-04-13 16:00:33下载
- 积分：1
