登录
首页 » VHDL » Triscend supports the use of the Model Technology ModelSim logic simulator for V...

Triscend supports the use of the Model Technology ModelSim logic simulator for V...

于 2023-07-10 发布 文件大小:50.87 kB
0 139
下载积分: 2 下载次数: 1

代码说明:

Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • digital_clock
    说明:  数字钟通过verilog实现,并且支持Modelsim仿真,通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)
    2020-06-18 05:00:02下载
    积分:1
  • XILINX平台DDR3设计教程
    从零开始的Xilinx DDR3 控制程序编写教程,利用MIS IP核通过自编逻辑实现对DDR3的读写,强烈推荐(This is a zero to start Xilinx DDR3 control program written tutorial, the use of MIS IP kernel through the self compiled logic to achieve DDR3 reading and writing, strongly recommended.)
    2018-06-05 21:28:45下载
    积分:1
  • FPGA_AD7822
    基于FPGA的AD转换控制器设计,AD7822,quartus II,verilog hdl(A Design of the A/D Convertion Control Module Based on FPGA)
    2011-08-26 15:06:18下载
    积分:1
  • sim_uart
    uart 收发器 verilog 代码,实现自收发功能 sys clk = 25m, baud 9600 停止位1, 无校验位; 代码实现了串口自收发功能,及把从 PC 收到的内容都发送会 PC, 其他波特率,自行修改代码即可,在 alter 的FPGA 上调试通过; (verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through )
    2010-10-10 21:49:46下载
    积分:1
  • VHDL--VGA
    此VHDL语言程序可以控制液晶屏幕任意动画播放(The VHDL language program can control the LCD screen any animation)
    2015-03-27 18:44:28下载
    积分:1
  • 多功能波形发生器VHDL程序与仿真 URAT VHDL程序与仿真 ASK调制与解调VHDL程序及仿真 LCD控制VHDL程序与仿真...
    多功能波形发生器VHDL程序与仿真 URAT VHDL程序与仿真 ASK调制与解调VHDL程序及仿真 LCD控制VHDL程序与仿真-Multi-function waveform generator and simulation of VHDL procedures URAT VHDL simulation procedures and ASK modulation and demodulation procedures and VHDL simulation program LCD control and simulation of VHDL
    2023-06-27 23:35:04下载
    积分:1
  • hard
    在Quartus中,利用FPGA例化的存储器实现程序的BOOTLOADER的搬移(In Quartus, the use of FPGA case of memory to achieve the program' s move BOOTLOADER)
    2020-09-27 20:17:46下载
    积分:1
  • 016_versat_updown_counter
    说明:  Verilog实现的加减法功能计数器,通过独立的自增自减信号控制计数器进行自增计数和自减计数(Function counter of addition and subtraction implemented by Verilog)
    2019-11-27 23:16:27下载
    积分:1
  • gg
    说明:  FPGA实现基带成型滤波器,升余弦滚降系数,多进制调制(FPGA)
    2010-12-20 17:55:18下载
    积分:1
  • ioRWTest
    C6000系列之6701开发板相关文件及说明(C6000 Series of 6701 development board-related documents and notes)
    2008-04-17 17:08:58下载
    积分:1
  • 696516资源总数
  • 106571会员总数
  • 2今日下载