登录
首页 » VHDL » 多功能波形发生器VHDL程序与仿真 URAT VHDL程序与仿真 ASK调制与解调VHDL程序及仿真 LCD控制VHDL程序与仿真...

多功能波形发生器VHDL程序与仿真 URAT VHDL程序与仿真 ASK调制与解调VHDL程序及仿真 LCD控制VHDL程序与仿真...

于 2023-06-27 发布 文件大小:221.90 kB
0 130
下载积分: 2 下载次数: 1

代码说明:

多功能波形发生器VHDL程序与仿真 URAT VHDL程序与仿真 ASK调制与解调VHDL程序及仿真 LCD控制VHDL程序与仿真-Multi-function waveform generator and simulation of VHDL procedures URAT VHDL simulation procedures and ASK modulation and demodulation procedures and VHDL simulation program LCD control and simulation of VHDL

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • inverter chain
    说明:  基于HSPICE实现的反相器链,并分析电路延时(Inverter chain based on HSPICE, and analyze circuit delay)
    2020-04-21 12:55:52下载
    积分:1
  • costas_DPSK
    采用costas环进行DPSK解调的程序。输入数据速率2.4Kbps,载波频率12KHz,采样率1.6MHz, 输入数据位宽12位,快捕带为799.617Hz(Costas ring using DPSK demodulation process. Input data rate 2.4Kbps, carrier frequency 12KHz, sampling rate 1.6MHz, the input data 12 bits wide, fast catching band is 799.617Hz)
    2014-06-09 21:50:42下载
    积分:1
  • 四位动态数码管显示数字时钟的分位和秒位。工具:Quartus ii 6.0 语言:VHDL...
    四位动态数码管显示数字时钟的分位和秒位。工具:Quartus ii 6.0 语言:VHDL-4 shows the number of dynamic digital tube digital clock and seconds bit. Tools: Quartus ii 6.0 Language: VHDL
    2023-08-13 03:20:02下载
    积分:1
  • 8051core-Verilog
    8051core-Verilog FPGA
    2021-02-02 21:59:59下载
    积分:1
  • 用VHDL编写的RS232串口的通信程序
    用VHDL编写的RS232串口的通信程序-Written with the VHDL serial RS232 communication program
    2022-05-06 01:41:31下载
    积分:1
  • 关于寄存器重命名register reallocation,VHDL
    关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL
    2022-02-09 20:31:31下载
    积分:1
  • GCD
    Verilog 最大公约数设计RTL级代码和芯片设计图(Verilog GCD Design and synthesis layout )
    2021-04-26 15:48:45下载
    积分:1
  • verilog 我自己写得按单脉冲发生器,通过了综合和仿真,和频率可变的正弦波发生器,...
    verilog 我自己写得按单脉冲发生器,通过了综合和仿真,和频率可变的正弦波发生器,-verilog I write by a single pulse generator, through the synthesis and simulation, and variable frequency sine wave generator,
    2022-04-19 00:17:00下载
    积分:1
  • DDS now to the use of more extensive relative bandwidth, frequency conversion ti...
    DDS在现在运用月来越广泛,在相对带宽、频率转换时间、相位连续性、正交输出、高分辨力以及集成化等方面都远远超过了传统频率合成技术所能达到的水平,为系统提供了优于模拟信号源的性能。利用DDS技术可以很方便地实现多种信号。在FPGA上实现的DDS-DDS now to the use of more extensive relative bandwidth, frequency conversion time, phase continuity, quadrature output, high-resolution and integration, and other aspects far more than the traditional frequency synthesizer technology can achieve the level To provide a superior analog signal source performance. DDS technology can be used very easily to a variety of signal. FPGA Implementation of DDS
    2022-02-12 02:47:38下载
    积分:1
  • sportswatch
    完整的跑表设计,时,分,秒都显示,希望能对大家有用,谢啦(Complete stopwatch design, hours, minutes, seconds, show, hoping to be useful for everyone,)
    2009-12-09 11:25:27下载
    积分:1
  • 696518资源总数
  • 105901会员总数
  • 40今日下载