-
串并转换程序，由串行输出转换为4位的并行输出
串并转换程序，由串行输出转换为4位的并行输出-String and the conversion process, from the serial output is converted to 4-bit parallel output
- 2022-04-12 06:17:43下载
- 积分：1
-
5
fpga paper function fff(fpga paper function)
- 2010-03-11 23:15:24下载
- 积分：1
-
FPGA
FPGA的学习指南，绝对经典，内容比较超值，我已经细心读过了，讲解清晰，快速入门。-FPGA-study guide, an absolute classic, the content of more value, I have carefully read, and to explain clearly, Getting Started.
- 2023-07-28 14:25:03下载
- 积分：1
-
jiaotongdeng
十字路口交通灯的单片机控制源代码 红黄绿三灯 还有数码管时间显示(Intersection traffic lights SCM source code red yellow three lights and LED time display)
- 2011-08-07 23:34:04下载
- 积分：1
-
Synopsys-tools-intruction
synopsys的主要的工具介绍，包括DC,PT,Formality等，对于初学IC设计者了解设计工具有很大帮助。(synopsys of the main tools for presentations, including DC, PT, Formality, etc., for the beginner tool for IC designers to understand the design of much help.)
- 2011-08-06 12:21:01下载
- 积分：1
-
Single-CPU
说明： 简单的单周期CPU设计，实现的指令有：算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)
- 2020-06-16 12:28:32下载
- 积分：1
-
FIR滤波器的基本Verilog代码实现
FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
- 2023-05-26 13:40:03下载
- 积分：1
-
pinlvji
使用FPGA测量频率大小，并且在数码管上进行显示(Frequency measurement using FPGA and display on digital tube)
- 2020-06-18 10:20:02下载
- 积分：1
-
第七次课--视频图像DCT处理及水印嵌入_2
说明： 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
利用双线性插值方法实现对图像640×480到1024×768的放大操作。
完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
-
ATEREAL EPM1270T144C5N CPLD
基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集原码 开发软件 Quartus II -ATEREAL EPM1270T144C5N CPLD-based pressure sensor data acquisition source Quartus II development software
- 2022-02-06 01:07:35下载
- 积分：1
