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uart
说明： fpga串口收发完整程序，Verilog语言。(FPGA configuration PLL complete program, Verilog language.)
- 2020-06-20 17:00:02下载
- 积分：1
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编译实现循环码的产生，用FOR循环分别对其中的码元进行设置。...
编译实现循环码的产生，用FOR循环分别对其中的码元进行设置。-Implementation cycle of the compiler generated code, respectively, using FOR Cycle one of the key element of the set.
- 2022-08-11 07:55:45下载
- 积分：1
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wide_cbf
宽带波束形成，设计FIR滤波器系数。带宽为500Hz--700Hz,采样率为3000Hz，对白噪声序列进行滤波，即得到有限带宽的宽带时域信号(Broadband beamforming design FIR filter coefficients. Bandwidth of 500Hz- 700Hz, sampling rate of 3000Hz, filtered white noise sequence, ie limited bandwidth broadband time domain signal)
- 2013-03-19 09:40:45下载
- 积分：1
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和picoblaze完全兼容的mcu ip core
和picoblaze完全兼容的mcu ip core-And PicoBlaze fully compatible mcu ip core
- 2023-08-22 23:25:04下载
- 积分：1
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Crack_QII72_FULL_License
Quartus II 7.2最完美的license破解器!(Quartus II 7.2 FULL and perfect License!)
- 2012-03-09 11:15:22下载
- 积分：1
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Cerradura
Conduct a digital system ( electronic lock ) using
hierarchic methodology .
An electronic lock is a device that allows access or
opening of a system , as long as the key or combination to enter match
with which it is predefined in said lock .
- 2014-10-10 15:41:14下载
- 积分：1
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can总线
说明： SJA1000的ip核和相关测试脚本,OPENCORES 下载(SJA1000 IP downloads from opencores)
- 2019-11-15 10:07:14下载
- 积分：1
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电子密码锁的vhdl编程实现，不知以前有没有人做过的。
电子密码锁的vhdl编程实现，不知以前有没有人做过的。-electronic locks VHDL programming, I wonder if the past is not done.
- 2022-06-19 03:31:21下载
- 积分：1
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adder8
8位加法器源代码，vivado实现编写。(8 adder Source, vivado achieve write.)
- 2015-12-01 20:35:55下载
- 积分：1
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ofdm_integration
整合的OFDM调制解调方法，matlab文件，modelsim仿真(Integration OFDM modulation and demodulation method, matlab file, modelsim simulation)
- 2012-09-03 17:13:35下载
- 积分：1
