登录
首页 » VHDL » FPGA

FPGA

于 2023-07-28 发布 文件大小:156.28 kB
0 82
下载积分: 2 下载次数: 1

代码说明:

FPGA的学习指南,绝对经典,内容比较超值,我已经细心读过了,讲解清晰,快速入门。-FPGA-study guide, an absolute classic, the content of more value, I have carefully read, and to explain clearly, Getting Started.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • mux21a
    在VHDL结构体中用于描述逻辑功能和电路结构的语句分为顺序语句和并行语句两部分,顺序语句的执行方式十分类似于普通软件语言的程序执行方式,都是按照语句的前后排列方式顺序执行的。(VHDL structure in the body used to describe the logic function and circuit structure of the order of statements and expressions are divided into two parts in parallel statement, modalities for the implementation of the order of statement is very similar to ordinary language software program implementation, are in accordance with the statements before and after the arrangement of the order implementation.)
    2008-12-24 18:25:20下载
    积分:1
  • High Speed dd
    说明:  (Springer Series in Advanced Microelectronics 51) Ayan Palchaudhuri, Rajat Subhra Chakraborty (auth.)-High Performance Integer Arithmetic Circuit Design on FPGA_ Architecture, Implementation and Desig
    2020-06-24 08:40:01下载
    积分:1
  • 20190717
    说明:  uart documentation, july 17, 2019. the document describes the basics of verilog programming and how to implement them on an fpga device
    2020-06-21 21:40:01下载
    积分:1
  • mdio
    使用verilog语言进行编码 完成mdio接口访问phy8201芯片的功能(Use verilog language to encode the mdio interface to access the function of phy8201 chip)
    2018-09-18 14:20:40下载
    积分:1
  • RAM存储器: 设定16 个8 位存储单元。如果read= 1 则dataout<=mem(conv_integer(address)). 如果write
    RAM存储器: 设定16 个8 位存储单元。如果read= 1 则dataout
    2022-08-05 20:01:41下载
    积分:1
  • tiny-dnn-1.0.0a2
    在zedboard上运行的神经网络架构,方便移植。(Run lenet-5 on zedboard)
    2020-06-23 19:00:02下载
    积分:1
  • VHDL language used hardware realize the serial communication of test code that c...
    用硬件VHDL语言实现的串口通信的试验代码,可用来代替单片机的工作对串口进行测试。-VHDL language used hardware realize the serial communication of test code that can be used to replace the work of single-chip serial port for testing.
    2022-06-01 13:40:50下载
    积分:1
  • ISE
    设计一4位比较器,画出门级电路图,用verilog语言完成设计。 (Design a four comparators, drawing out level circuit diagram, complete the design using verilog language. )
    2015-12-11 21:16:12下载
    积分:1
  • ROM的4位的话。
    4 bit ROM for Quartus
    2022-01-30 19:14:13下载
    积分:1
  • keyscan
    利用VHDL语言编写的4*4键盘扫描程序,经过测试,可以放心使用。(Using VHDL language 4* 4 keyboard scanning procedures, tested, safe to use.)
    2013-09-28 21:48:45下载
    积分:1
  • 696518资源总数
  • 105547会员总数
  • 4今日下载