-
人脸识别（3D）
说明： 基于高清视频的3D人脸识别源代码，四万多行，经过FPGA实际验证，最近调试完毕。(The source code of 3D face recognition based on HD video, more than 40,000 lines, has been verified by the actual FPGA, and has been debugged recently.)
- 2019-07-01 16:22:46下载
- 积分：1
-
这个代码是Verilog HDL。
this Code is in verilog HDL.
This Code is for piplined processor with 4 opcode.
this will work in three cycle latch, decode and exicute..
test bench for xilinx ise is laos given
- 2022-02-12 09:39:12下载
- 积分：1
-
liyuanlnx_key_beep
说明： FPGA按键加蜂鸣器实验：
加延时防抖+蜂鸣器(Experiments of keys and buzzers in FPGA)
- 2020-06-22 04:00:01下载
- 积分：1
-
gam7
FPGA Implementation ofLow Power 64-Point
Radix-4 FFT Processor for OFDM System
- 2011-01-22 11:45:44下载
- 积分：1
-
wom_kg
ϵͳʱ
- 2006-03-13 15:09:50下载
- 积分：1
-
使用vhdl实现的1024点的FFT算法
使用vhdl实现的1024点的FFT算法-Using vhdl implementation of the 1024-point FFT algorithm
- 2022-01-30 20:38:46下载
- 积分：1
-
VerilogHDL_DC_Motor_control
采用Verilog HDL语言编写的直流电动机控制系统，主要完成直流电动机的速度控制，典型的三闭环(位置、转速和电流反馈)直流电机控制系统，对控制类相关的学习者价值很高(Using Verilog HDL language of the DC motor control system, mainly the completion of DC motor speed control, a typical three-loop (position, speed and current feedback) DC motor control system for control-type high-value related to the learner)
- 2008-01-10 23:34:29下载
- 积分：1
-
FSK调制通信系统的程序，比较实用，包括有限..
通信系统的FSK调制程序，比较实用，包括完整的工程-FSK modulation communication system procedures, more practical, including the complete works
- 2023-01-02 07:10:03下载
- 积分：1
-
shuzishizhong
这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)
- 2013-12-10 22:21:55下载
- 积分：1
-
2
说明： ADV7179芯片的驱动程序，基于FPGA硬件实现，已经验证可以使用(ADV7179 chip drivers, FPGA-based hardware implementation has been verified using)
- 2011-02-21 16:06:56下载
- 积分：1
