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this the of the javabeanstm架构规范的企业。企业……
This the specification of the Enterprise JavaBeansTM architecture.The Enterprise JavaBeans
architecture is a component architecture for the development and deployment of componentbased
distributed business applications. Applications written using the Enterprise JavaBeans
architecture are scalable, transactional, and multi-user secure. These applications may be written
once, and then deployed on any server platform that supports the Enterprise JavaBeans
specification.-This the specification of the Enterprise JavaBeansTM architecture.The Enterprise JavaBeans architecture is a component architecture for the development and deployment of componentbased distributed business applications. Applications written using the Enterprise JavaBeans architecture are scalable, transactional, and multi-user secure. These applications may be written once, and then deployed on any server platform that supports the Enterprise JavaBeans specification.
- 2023-01-29 18:10:04下载
- 积分：1
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Guide!
win32汇编资料 教程!-Guide!
- 2022-02-13 07:23:00下载
- 积分：1
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BEA WebLogic server_一
BEA WebLogic Server_ a
- 2022-12-21 04:40:03下载
- 积分：1
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Java学习从入门到精通，非常适合初级java爱好者
Java学习从入门到精通，非常适合初级java爱好者-Java learning from entry to the proficient and very suitable for the junior java lovers
- 2022-08-03 14:09:42下载
- 积分：1
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support acids phone use. To produce their own electronic book software
支持JAVE的手机用的.自己制作电子书的软件-support acids phone use. To produce their own electronic book software
- 2023-02-14 04:15:04下载
- 积分：1
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for beginners can look at the future, they will choose some of the better point...
对于初学者可以看一看，将来还会挑选一些更好一点的内容上传。下载后可以直接看。-for beginners can look at the future, they will choose some of the better point upload. After downloading can look directly.
- 2022-04-17 02:06:20下载
- 积分：1
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LED驱动器的例子
LED driver example
- 2022-01-24 16:57:17下载
- 积分：1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分：1
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c语言的上课讲义，简单明了，从计算机语言数据结构到c的语法、算法...
c语言的上课讲义，简单明了，从计算机语言数据结构到c的语法、算法-class lectures, concise language from the computer data structure to C syntax, the algorithm
- 2022-01-31 10:48:24下载
- 积分：1
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LDAP资料，包括原理，功能，树状结构LDAP和基于RDBMS的LDAP的比较...
LDAP资料，包括原理，功能，树状结构LDAP和基于RDBMS的LDAP的比较-LDAP information, including the principle, function, tree structure of LDAP and LDAP-based RDBMS comparison
- 2022-08-11 22:17:10下载
- 积分：1
