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some important data structure Daquan
一些重要的数据结构大全-some important data structure Daquan
- 2023-03-28 04:40:03下载
- 积分：1
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本书荣获2005年第十五届Jolt通用类图书震撼大奖。 继 Effective C++ 之后，Scott Meyers 于 1996 推出这本「续集」。本书与现...
本书荣获2005年第十五届Jolt通用类图书震撼大奖。 继 Effective C++ 之后，Scott Meyers 于 1996 推出这本「续集」。本书与现今之 C++ 标准规格几乎相同。可能变化的几个弹性之处，Meyers 也都有所说明与提示。-the book won the 2005 session of the 15th General Books Jolt Awards shock. Following the Effective C, Scott Meyers in 1996 to launch the "sequel." The book"s C with the current standard is almost the same. Several possible changes in flexibility, Meyers also has suggested and described.
- 2022-03-09 23:19:23下载
- 积分：1
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这是一篇讲解蚂蚁算法的文章。我看到上载分类里有文章、书籍类别，并不仅限于源代码，就上载了这个文章，格式为PDF文件。我读过，很好。是英文的。...
这是一篇讲解蚂蚁算法的文章。我看到上载分类里有文章、书籍类别，并不仅限于源代码，就上载了这个文章，格式为PDF文件。我读过，很好。是英文的。-This is an ant algorithm on the article. I saw on the classification there are articles, books category and is not limited to source code, on the last set of this article, PDF format for the document. I read, very good. Is in English.
- 2022-03-29 05:38:29下载
- 积分：1
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A Low
A Low-Power ASIC Implementation of 2Mbps Antenna-Rake Combiner for WCDMA with MRC and LMS Capabilities.pdf
- 2022-05-12 15:15:38下载
- 积分：1
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GB8567
国标规定的软件工程相关内容。
软件研发团队必备参考文档。...
GB8567
国标规定的软件工程相关内容。
软件研发团队必备参考文档。-GB8567 GB provides software engineering-related content. Software R
- 2022-11-25 04:00:03下载
- 积分：1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分：1
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verilog编程参考用书
verilog编程参考用书-Verilog programming reference book
- 2022-02-09 13:24:30下载
- 积分：1
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软件工程――――实训医院患者监护管理系统0层图
软件工程――――实训医院患者监护管理系统0层图-Soft-care management system for public hospital patients 0 layer diagram
- 2022-03-02 13:52:55下载
- 积分：1
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易数玄机
易数玄机-陈抟 很好的一本五代宋初著名异术学家的占卜电子书，-YiShuXuanji
- 2023-08-05 08:35:03下载
- 积分：1
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c#教程，有关DirectX9游戏制作 的
c#教程，有关DirectX9游戏制作 的-Guide, produced by the DirectX9 games
- 2022-08-25 00:04:07下载
- 积分：1
