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Farrow
说明： matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)
- 2021-03-28 22:29:11下载
- 积分：1
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电梯
利用verilog编写的电梯程序，实现基本的电梯运行功能(Elevator program written by Verilog)
- 2018-11-25 11:39:50下载
- 积分：1
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用verilong hdl语言编写的数据采样程序，A/D采用的是TLC5260
用verilong hdl语言编写的数据采样程序，A/D采用的是TLC5260-Verilong hdl language used data sampling procedures, A/D using the TLC5260
- 2023-04-01 09:25:04下载
- 积分：1
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Tutorijal 6
Ovo sto saljem je tutorijal 7 sa vhdlom
- 2018-12-22 06:47:31下载
- 积分：1
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asynchronous-fifo
同步fifo的调用程序，调用Quartus II 9.0 (32-Bit)中的fifo模块(Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module)
- 2013-08-23 21:58:56下载
- 积分：1
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apb.v
AMBA总线apb总线的verilog代码以及相关的中断控制。(AMBA bus apb bus verilog code and associated interrupt control.)
- 2021-04-17 20:38:53下载
- 积分：1
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7_to_1-LVDS-dispaly-from-FLASH
该代码是基于verilog 实现的代码，可以用于对接受1080P的LVDS视频数据并处理后显示到各种规格的LCD屏幕上，且支持从FLASH中读取BMP的图片数据并实时显示到LCS屏幕(The code is based on the code verilog achieve, it can be used for receiving LVDS 1080P video and data processing displayed on a variety of LCD screen, and support for reading data the FLASH BMP images and real-time display to the LCS screen)
- 2016-02-18 14:06:22下载
- 积分：1
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sysgen_gs
Xilinx system generator
- 2020-12-25 15:39:04下载
- 积分：1
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GAL16V8(fangzhen74LS138)
GAL16V8(仿真74LS138),试验通过。包括able及jed文件。对pcb印板设计时，对简化走线特别有用。简单的修改GAL16V8程序，可灵活地进行地址译码修改。(GAL16V8 (simulation 74LS138), test passed. Including the able and jed file. Printed on the pcb board design, especially useful to simplify alignment. Simple modifications GAL16V8 program, the flexibility to change the address decoding.)
- 2011-01-26 20:43:01下载
- 积分：1
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source
ＦＰＧＡ与ＳＤＲＡＭ 的 ＶＨＤＬ 接口设计(ｔｈｅ interface of FPGA and SDRAM)
- 2012-03-28 22:17:19下载
- 积分：1
