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dds32_1
说明： 频率合成器实例模块设计。频率分辨率为32位DDS的VHDL程序(Frequency synthesizer module design example. 32-bit DDS frequency resolution of the VHDL program)
- 2011-04-14 13:45:22下载
- 积分：1
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tcdg
Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorithms existing, and I feel there is a need to understand how they work. So this text explains a number of popular encryption algorithms and makes you look at them as mathematical formulas.
- 2014-01-29 15:57:35下载
- 积分：1
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This book is on the Xilinx
这本书是关于Xilinx公司开发的ISE工具的中文教程，适合于初学FPGA设计的人使用，全书内容丰富，共包括9章，通过此书的学习可以了解并掌握FPGA的设计流程及设计方法。-This book is on the Xilinx
- 2022-05-14 07:46:13下载
- 积分：1
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this document is in two MAXplusII environment through the development and operat...
此两文件是在MAXplusII环境下开发并运行通过的VHDL文件，实现了并串口转换功能。-this document is in two MAXplusII environment through the development and operation of the VHDL documents, and the realization of serial conversion function.
- 2022-02-26 14:17:56下载
- 积分：1
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maxplus2 VHDL development environment for the preparation of the keyboard proced...
maxplus2为开发环境 vhdl编写的 键盘 程序-maxplus2 VHDL development environment for the preparation of the keyboard procedures
- 2022-02-14 21:32:29下载
- 积分：1
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真正成为一个母版页，然后必须了解和使用DHTML。这里省…
成为真正的网页制作的高手的话,必须了解并使用DHTML.这里提供了最好的手册和文档.-become truly a master pages, then have to understand and use DHTML. Here to provide the best manuals and documents.
- 2023-03-13 00:40:03下载
- 积分：1
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一个快速和简单的斯巴达教程3
A quick and simple Spartan 3 tutorial
- 2023-03-19 05:05:04下载
- 积分：1
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Copy
说明： this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device
- 2020-06-21 21:00:02下载
- 积分：1
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ethernet-verilog
非常详细的千兆以太网MAC verilog代码，可以供硬件设计时有关网络的开发参考(Very detailed Gigabit Ethernet MAC verilog code, can be used for hardware design of the network to develop a reference)
- 2020-09-19 11:27:57下载
- 积分：1
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freeDev数字应用开发板中的七段数码管的IP核的verilog实现
freeDev数字应用开发板中的七段数码管的IP核的verilog实现-freeDev digital application development boards in the seven-segment digital tube of the IP core implementation of the verilog
- 2022-01-31 19:57:07下载
- 积分：1
