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二进制串行-1计数器

于 2005-07-08 发布 文件大小:27KB
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  大学计算机数字逻辑实验作业 用Multisim仿真软件编写 计数器 用双D触发器74Ls74构成四位二进制串行计数器 二分频计数原理(University computer digital logic operations using Multisim experimental simulation software used to prepare counter-D Trigger 74Ls74 constitute four serial binary frequency counter two hours counting Principle)

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