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用Verlog HDL编写的数字钟程序，包含时，分，秒，进位，解码，扫描显示等功能。...
用Verlog HDL编写的数字钟程序，包含时，分，秒，进位，解码，扫描显示等功能。-Written by Verlog HDL ，a digital clock program, including hours, minutes, seconds, into the place, decoding, scanning display.
- 2023-02-05 04:55:03下载
- 积分：1
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在ise10.1.3 Xilinx PicoBlaze的应用开发。
Xilinx PicoBlaze application developed in ISE10.1.3.
- 2023-07-28 07:25:03下载
- 积分：1
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myAdc9248
CycloneIV控制采样芯片AD9248-20MHz，VHDL语言(CycloneIV control sampling chip AD9248-20MHz, VHDL language)
- 2017-01-31 21:55:26下载
- 积分：1
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5956474temperature
DS18b20 temperature sensor vhdl code
- 2010-07-04 03:46:44下载
- 积分：1
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capture-using-SCCB-and-FPGA
利用SCCB和FPGA实现视频采集的论文，对相关开发人员具有很强的参考价值！
(FPGA implementation using the SCCB and video collection of the papers, the relevant developer has a strong reference value !
)
- 2013-09-29 15:37:52下载
- 积分：1
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CO_2
说明： 激光测速研究，主要介绍多普勒激光测速知识(Laser velocimetry study introduces laser-Doppler velocimetry knowledge)
- 2008-10-24 22:29:44下载
- 积分：1
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fifo
一个FIFO产生程序，主要是一个格雷码的加法器(A FIFO generation process, is primarily a gray code adder)
- 2011-08-28 10:39:31下载
- 积分：1
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adder.ripple
an 16 bit ripple carry adder
- 2012-11-02 23:20:33下载
- 积分：1
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time_frequency_analysis
一种合并频率的方法对时频分析及其有用所以才上传(a fast combination)
- 2013-12-04 10:13:24下载
- 积分：1
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verilog HDL语言编写的键盘扫描程序，考虑以确定关键的博…
Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, once the judge has said there is a classified as low-key is pressed, stop the scan and to maintain the current line-line state, and then read out line state to get the current keys key codes to wait for key pop-up: To detect the lines at all out into a high level after the re-start the scanning process, waiting for the next key.
- 2022-05-07 15:33:47下载
- 积分：1
