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verilog_median_filter
图像处理的中值滤波器,使用verilog开发环境编程实现。(Verilog development environment programming median filter)
- 2016-01-24 16:54:32下载
- 积分:1
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电子表的实现
这是一个数字逻辑课程的电子表的实现,利用VHDL语言实现,初学者可以完全掌握,很有帮助。
- 2022-08-20 05:43:08下载
- 积分:1
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BCH3
BCH3.c,提供m<21以下的所有码长的BCH编解码模块。以供大家参考。谢谢(BCH encoder&decoder GF(2^m) m<21)
- 2021-01-26 11:58:36下载
- 积分:1
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traffic_lights
交通灯控制器控制红(r)、绿(g)、黄(y)三种不同颜色的交通灯,这三种不同颜色灯的亮、灭分别由三个定时器(timer1、timer2、timer3)控制;
当某个定时器工作时,它所控制的交通灯亮,直到设定的定时时间到(该定时器状态由’0’变’1’),交通灯跳转到另一种状态;
clk是脉冲控制端(图中未标出);reset是异步复位端,复位状态为红色交通灯亮;
输出端r、g、y分别表示三种颜色交通灯的亮、灭状态。
( traffic light controller control red (R), green (g), yellow (y) three different colors of traffic lights, three different colors of bright lights, off by three timer (Timer1, Timer2, Timer3 ) control When a timer work, it controls the traffic lights, until the set timing (the timer status ' 0 ' for ' 1' ), traffic lights Jump to another state clk is the pulse control terminal (not shown) reset is asynchronous reset terminal, the reset state for the red traffic lights output terminal r, g, y represent the three colors of traffic lights bright, the off state.)
- 2020-12-19 15:09:10下载
- 积分:1
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主要是通过Altera公司的Cuclone系列的FPGA
主要是通过Altera公司的Cuclone系列的FPGA-EP1C3T144C8产生余弦波的源代码 基于LPM-ROM余弦波一周期含有256个10位数据;-Mainly through Altera s Cuclone series of FPGA-EP1C3T144C8 cosine wave generated source code based on the LPM-ROM cosine wave of one cycle containing 256 10-bit data
- 2023-06-17 01:00:03下载
- 积分:1
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shuzifujieqi
主要给出准循环的LDPC码编码实现方法,译码方法选择,并给出了帧同步的解决方法(Give the main quasi-cyclic LDPC codes achieve coding method, decoding method of selection, and give the frame synchronization solution)
- 2009-03-14 17:22:33下载
- 积分:1
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DE2 SOPC LCM
DE2 S O P C 用硬件语言 描述地 开发板上测试 CLM模块 实现视频传输-DE2 SOPC LCM
- 2022-07-01 11:31:51下载
- 积分:1
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dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.
dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.
- 2023-03-22 17:40:04下载
- 积分:1
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baud
说明: 将外部的输入的6Mhz的信号分成为频率为153600hz的信号(The external input signal divided into 6Mhz 153600hz signal frequency)
- 2010-04-11 23:16:18下载
- 积分:1
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PCIE资料和仿真教程1-6
PCIE仿真设计教程1-6,我帮大家收集到一起了(PCIE simulation design tutorial 1-6, I help you gather together.)
- 2020-11-09 19:29:46下载
- 积分:1