基于FPGA Verilog驱动线性TCD1254GFG传感器驱动程序，驱动频率2MHz，帧率333帧每秒，曝光时间调节范围0-3000us，带数据读取时序1MHz。(The driver of linear TCD1254GFG sensor is driven by Verilog based on FPGA. The driving frequency is 2MHz, the frame rate is 333 frames per second, the exposure time adjusting range is 0-3000us, and the reading time sequence is 1MHz.)
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多周期MIPS system vivado实现(Multi-cycle MIPS system vivado)
学校实验，用Verilog实现的单周期CPU,分别实现I型、R型、指令，使用的工具为ISE(School experiments, using Verilog to achieve a single cycle CPU, respectively, to achieve I type, R type, instruction, the use of tools for ISE)
CRC24的verilog实现,LTE的3GPP 36.212里面对应的CRC添加(the implementation of CRC24 in verilog)
基于AHB总线的sram控制器，带有memory bist(SRAM controller based on AHB bus)
基于芯片5CSEBA6U2317，实现按键控制LED灯闪的速度的Verilog实现。(Realize the Verilog realization of the flow lamp.)
Turbo编码的FPGA实现，采用了（7，5）RSC编码和循环移位交织，帧长度128bit(The FPGA implementation of Turbo coding adopts (7, 5) RSC coding and cyclic shift interleaving, and the frame length is 128bit.)
SystemVerilog 写的APB总线接口的uart 代码，带testbench.(Uart code of APB bus interface written by SystemVerilog, with testbench.)
实现SVPWM的算法实现和仿真，基于FPGA平台用VHDL语言编写(Realization and Simulation of algorithm for realizing SVPWM)
《基于FPGA的单精度浮点数乘法器设计》详细介绍了按照IEEE754标准在FPGA上实现单精度浮点加减乘除的方法(The design of single precision floating point multiplier based on FPGA introduces in detail the way of realizing single precision floating point addition, subtraction and multiplication and division based on IEEE754 standard on FPGA.)
滤波器的实现，总共为4种，是简单的coif3滤波器的实现方法(The implementation of the filter, a total of 4, is a simple coif3 filter implementation method)
quartus ii项目文件包，功能是改进的booth乘法器，节省时钟，已完成仿真。(This zip file contains a quartus ii project, which can fufill multiple function. It is done by using a modified booth multiplier.)
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