altera公司IP核使用手册.PDF
altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation
- 2020-12-05下载
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SVPWM算法详解_已标注重点_
详细的讲解了SVPWM的过程，及其仿真，很适合初学者或(37)即磁链空间矢量可以等效为电压空间矢量的积分,如果能够控制电压空间矢量的轨迹为如式(3.4)所示的圆形矢量,那么磁链空间矢量的轨迹也为圆形。这样,电动机旋转磁场的轨迹问题就可以转化为电压空间矢量的运动轨迹问题。进一步分析,由式(3.3)(3.5)(3.7)可以得到公式(3.8)∫-+yy(38)对电压积分,利用等式两边相等的原则有(39)其中,v为电机磁链的幅值,即为理想磁链圆的半径。y当供电电源保持压频比不变时,磁链圆半径v是固定的。在 SVPWM控制技术中,是取以y为半径的磁链圆为基准圆的。32逆变器电压的输出模式图32给出了电压源型PWM逆变器—异步电动机示意图14。昇步电动机定子绕组YY图3.2PWM逆变器电路(1~6为GBT)对于180°导电型的逆变器来说,三个桥臂的六个开关器件共可以形成8种开关模式。用分别标记三个桥臂的状态,规定当上桥臂器件导通时桥臂状态为1,下桥臂导通时桥臂状态为0,这样逆变器的八种开关模式对应八个电压空间矢量,其中为直流侧电压在逆变器的八种开关模式中,有六种开关模式对应非零电压空间矢量,矢量的幅值为一;有两种开关模式对应的电压矢量幅值为零,称为零矢量。当零矢量作用于电机时不形成磁链矢量;而当非零矢量作用于电机时,会在电机中形成相应的磁链矢量。对于每一个电压空间矢量,可由图32求出各相的电压值,再将各相的电压值代入式(3.3),可以求得电压空间矢量的位置。下面以开关状态)=(、0、0)为例,即开关导通,其余关断。逆变电路的形式可以变为B相和C相并连后再和A相串连的形式,易得将其数值代入式(33),可得采用同样的方法可以得到如表31所示的逆变器空间电压矢量。表31逆变器的不同开关状态对应的空间矢量表相电压矢量表达式定子电压开关状态(Us大小为空间矢量A相B相C相0000000101001110010111100由于 SVPWM控制的是逆变器的开关状态,在实际分析逆变器一电动机系统时,可以通过分析逆变器输出的电压空间矢量来分析电机定子电压的空间矢量,下面给出证明。设逆变器输出的三相电压为、,由图3.2可求出加到电机定子上的相电压为(310)其中,为电机定子绕组星接时中点0相对于逆变器直流侧点的电位。电机定子电压空间矢量为(311)而由三角函数运算知++因此,逆变器输出的电压空间矢量为(312)由式(3.12)可知,在PWM逆变器一电动机系统中,对电机定子电压空间矢量的分析可以转化为对逆变器输出电压空间矢量的分析。这时,在求解表3.1时,可以直接利用逆变器输出的电压合成得到,即A,B,C三相输出电压值只有一和-—两个值。当逆变器输出某一电压空间矢量时,电机的磁链空间矢量可表示为y =y3.13)其中,W为初始磁链空间矢量;△为的作用时间。当为某一非零电压矢量时,磁链空间矢量y从初始位置出发,沿对应的电压空间矢量方向,以为半径进行旋转运动,当为一零电压矢量时,W=y,磁链空间矢量的运动受到抑制。因此合理地选择六个非零矢量的施加次序和作用时间,可使磁链空间矢量顺时针或逆时针旋转形成一定形状的磁链轨迹。在电机控制当中尽量使磁链轨迹逼近正多边形或圆形。同时,在两个非零矢量之间按照一定的原则,比如开关次数最少,插入一个或多个零矢量并合理选择零矢量的作用时间,就能调节ψ的运动速度。33SWPM的具体实现方法在实际应用中,应当利用 SVPWM自身的特点找到控制规律,避开复杂的数学在线运算,从而较为简单的实现开关控制,本节将给出实现 SVPWM的具体方法。根据3.2节中给出的不同开关状态组合可以得到如图33的电压空间矢量图C图3.3 SVPWM矢量、扇区图通常在矢量控制的系统当中,根据控制策略,进行适当的巫标变换,可以给出两相静止坐标系即(a,B)坐标系电压空间矢量的分量,g,这时就可以进行 SVPWM的控制,具体要做以下三部分的工作如何选择电压矢量。2.如何确定每个电压矢量作用的时间。3.确定每个电压矢量的作用顺序3.3.1电压空间矢量的空间位置这里需要引入扇区的概念,将整个平面分为六个扇区。如图3.3所示,每个扇区包含两个基本矢量,落在某个扇区的电压空间矢量将由扇区边界的两个基本电压空间矢量进行合成。在确定扇区时,引入三个决策变量A,B,C。根据给出的待合成的空间矢量的两个分量,p来决定A,B,C的取值,有以下关系式所在扇区的位置为当N取不同的值对应的扇区位置如图3.3所示,这样给定一个空间电压矢量就可以确定其所在的扇区。33.2电压空间矢量的合成扇区确定之后,就可以利用扇区边界上的两个基本矢量合成所需的矢量在合成过程中应当使得两个基本矢量的合成效果接近于期望矢量的效果。于是采用伏秒平衡的原则,以图3.3所示的第Ⅲ扇区为例,以a尸轴为基准,将两个基本矢量向aB轴上投影,应当有轴:=||+尸轴其中,为对应电压矢量作用的时间(=),为采样周期,通常为PW的调制周期。且|=||=-。求解上面两式可以得到这两个基本矢量的作用时间如式3.14(314)通过上面的方法即可以确定基本矢量的作用时间,当需要合成的矢量位于各个不同的扇区时都存在如上的运算。通过对每个扇区基本矢量动作时间的求解不难发现它们都是一些基本时间的组合。所以给出几个基本的时间变量x,Y,Z。定义√(315)通过计算可以得到在每个扇区内的基本矢量动作时间,(由于五段和七段式的实现方法不同,所以这里没有考虑矢量的动作顺序,仅按照逆时针方向)。设每个刷区的两个基本矢量动作的时间为于是可以得到矢量动作时间表3,2表3.2的对应关系表扇区ⅣV在实际的应用中当给定的电压值太大时会出现过调制的情况,即+>。此情况出现时,还要对上述计算出来的电压矢量的作用时间进行调整,具体方法如式3.16所示。(316)即为调整后的动作时间。在一个P啊M周期内除了非零电压矢量的作用,还要有零电压矢量的作用,零电压矢量包括对于这两个矢量的作用时间,以及开关的动作顺序,取决于采用的SPwM是五段式还是七段式,3.3节将对这两种PWM形式进行详细的介绍3.4 SVPWM的硬件实现和软件实现TI公司的TM320LF2407A系列的DSP内部有硬件来实现 SVPWM,由于每个PWM周期被分为五段,因此也被称为五段式的 SVPWM。在每个PWM调制周期内,开关状态有五种,且关于周期中心对称。而七段式的SvPM在每个PWM调制周期内有七种开关状态,需要运用软件进行实现,因此也被称为 SVPWM的软件实现。需要注意的是,无论哪种方法,所遵循的基本原则是开关动作次数最少,每个开关在一个周期内最多动作两次。3.4.1五段式 SVPWM对于五段式的 SVPWM,只在PMM周期的中间插入零矢量,具体采用哪一个由硬件根据旋转方向和开关动作次数最少的原则自行决定。例如在第Ⅲ扇区内,如果旋转方向为逆时针时针,则先动作,后动作以此类推,动作时间可以直接采用表3.2中的数据即可,然后选择零矢量(硬件决定)即可使开关次数最少。对于五段式PWM而言,零矢量作用的时间可以表示为:根据上述的配置原则,在每个扇区内开关动作的示意图如图34所示202ⅣV/1Ⅵ图34每个扇区内的开关动作示意图每个TMS320LF2407A的事件管理器EV模块都具有十分简化的电压空间矢量PWM波形产生的硬件电路。编程时只需进行如下的配置2●设置 ACTRX寄存器用来定义比较输出引脚的输出方式,决定高电平还是低电平有效,正反转,所在扇区等。●设置COMC0Nx寄存器来使能比较操作和空间矢量PWM方式,并且把 CMPRX的重装条件设置为下溢●将通用定时器1或2,4或5设置成连续增/诚计数模式,并启动定时器。然后给据在两相静止(a6)坐标系下输入到电机的电压空间矢量,分解为,确定如下的参数●所期望的矢量所在的扇区。根据 SVPWM的调制周期计算出两个基本的空间矢量和零矢量作用的时间
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