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学生基本Verilog
basic verilog for students
- 2022-09-22 04:00:04下载
- 积分：1
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pdf
说明： 一种基于FPGA的调频连续波方位向多通道
FMCW SAR的实时成像信号处理方法及FPGA，包
括：步骤一、计算重构矩阵；步骤二、重构方位向
多通道数据，包括：步骤2 .1、对各个通道的回波
数据沿方位向分别间隔补零，并进行方位向傅里
叶变换；步骤2 .2、将方位向傅里叶变换之后各个
通道方位向相同位置的点组合为一个向量并与
重构矩阵相乘，得到重构完成的方位向数据；(An azimuth multichannel FMCW based on FPGA
FMCW SAR real-time imaging signal processing method and FPGA, package
Including: Step 1: calculate the reconstruction matrix; step 2: reconstruct the orientation
Multichannel data, including: step 2.1, echo of each channel
The data is compensated with zero along the azimuth direction respectively, and the azimuth Fourier is carried out
Step 2.2, after the azimuth Fourier transform
The points of the same position in the channel azimuth are combined into a vector and are connected withThe reconstruction matrix is multiplied to get the reconstructed azimuth data
Step 2.3. Repeat step 2.3 for the data of different distance gates)
- 2020-02-07 19:47:41下载
- 积分：1
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用于压缩感知。OMP 是一种算法
用于压缩感知。OMP 是一种算法
- 2023-04-30 08:30:04下载
- 积分：1
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等精度频率计的verilogHDL的实现,我花了好长时间才写的哦
等精度频率计的verilogHDL的实现,我花了好长时间才写的哦
- 2022-06-28 09:27:01下载
- 积分：1
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VHDL_count 从 0 到 9 4 7 段 LED 显示 4 脉冲使 （đếm 慈 0 đến 9 hiển 施耐 4 带领 7 đoạn với 4 xung 启用）
VHDL_count 从 0 到 9 4 7 段 LED 显示 4 脉冲使 （đếm 慈 0 đến 9 hiển 施耐 4 带领 7 đoạn với 4 xung 启用）
- 2022-05-29 10:17:32下载
- 积分：1
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Altera in the official line on the SOPC custom component (PWM) of the examples a...
Altera官网上关于SOPC中自定义组件（PWM）的实例，官网上现在没了。。可很多书上都在用-Altera in the official line on the SOPC custom component (PWM) of the examples are not the official line. . Can be a lot of books are in use. . .
- 2022-02-04 13:32:48下载
- 积分：1
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通过VHDL语言的例子，乒乓球运动的FPGA原型样机（2章）是
应用背景FPGA原型的VHDL例子提供一系列清晰，易于遵循的快速代码开发模板；大量的实际例子来说明和强化的概念和设计技术；现实可实施的项目和测试在Xilinx原型板；深入探索和Xilinx PicoBlaze软核微处理器。关键技术本书采用“做中学”介绍VHDL和FPGA技术的概念和设计人员通过一系列的实验方法。
- 2022-08-13 14:19:44下载
- 积分：1
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16位的移位寄存器，加上testbench,可以在modelsim里面运行~
16位的移位寄存器，加上testbench,可以在modelsim里面运行~-16 of the shift register and testbench, modelsim the inside running ~
- 2023-07-15 21:45:02下载
- 积分：1
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counter (2)
This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.
- 2017-07-18 19:24:12下载
- 积分：1
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ComChange-12061629
说明： 并行读写14路串口数据，数据被写入FIFO，在收到读写信号后，SPI发送数据出去(Parallel read and write 14 serial port data, SPI send data)
- 2019-03-13 01:38:44下载
- 积分：1
