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RS_CC_ENC
OFDM系统新型CC编解码的verilogHDL设计,与RS编码级联,经测试误码率性能提高(OFDM system verilogHDL new CC codec design, coding and RS cascade, tested BER performance improvement)
- 2020-12-31 10:58:59下载
- 积分:1
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ISPPCBforFPGA
Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB(Xilinx, Altera, ARM, AVR, S52, Lattice series FPGA download cable circuit diagram and PCB)
- 2009-12-14 16:55:35下载
- 积分:1
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second7-02
在quartusII环境下采用对编解码芯片HD6408和HD6409驱动的方式实现曼彻斯特编解码(Environment in quartusII codec chip used on the HD6408 and HD6409-driven way to achieve encoding and decoding of Manchester)
- 2020-11-02 10:19:53下载
- 积分:1
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FPGA design of the guiding principles, it is classic! Want to give everyone easy
FPGA设计的指导原则,很经典的!希望给大家方便-FPGA design of the guiding principles, it is classic! Want to give everyone easy
- 2023-03-11 18:40:04下载
- 积分:1
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adder2
此源代码是基于Verilog语言的持续赋值方式定义的 2 选 1 多路选择器 、阻塞赋值方式定义的 2 选 1 多路选择器、非阻塞赋值、阻塞赋值、模为 60 的 BCD码加法计数器 、模为 60 的 BCD码加法计数器、BCD码—七段数码管显示译码器、用 casez 描述的数据选择器、隐含锁存器举例 ,特别是模为 60 的 BCD码加法计数器,这是我目前发现的最优源代码,应用于解码器领域。(This source code is based on the Verilog language define the continued assignment of 2-to-1 multiplexer, blocking assignments define the 2-to-1 multiplexer, non-blocking assignments, blocking assignments, module code for the addition of 60 BCD counters, BCD code module for the addition of 60 counters, BCD code- seven-segment LED display decoder, the data described by casez selector, for example hidden latch, in particular, the BCD model code for the addition of 60 counters, this is my found that the best current source code, the decoder used in the field.)
- 2010-10-30 15:14:06下载
- 积分:1
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cycle_measure
测量周期,此程序已经在EP2C板子上成功实现(mesure cycle)
- 2013-08-29 16:09:17下载
- 积分:1
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CPUdesign
说明: 计算机组成原理实验多时钟周期CPU设计,包含VHDL代码的设计,实验电路图,实验详细截图。(Computer component experiments designed more CPU clock cycles, including VHDL code design, test circuit, test detailed screenshots.)
- 2020-09-07 19:28:05下载
- 积分:1
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422
串口收发,实现可调波特率的串口通信,verilog源码(Serial port and transceiver)
- 2021-04-07 15:19:01下载
- 积分:1
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8b10bEncoderDecoder-SourceCode (1)
lattice的官方8b10b代码, 1012年版本,diamond3.5编译。(lattice 8b10b encoder decoder code)
- 2020-08-31 14:58:10下载
- 积分:1
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MAX48_cn
MAX481、MAX483、MAX485、MAX487-MAX491以及
MAX1487是用于RS-485与RS-422通信的低功耗收发器,
每个器件中都具有一个驱动器和一个接收器(The MAX481, MAX483, MAX485 The MAX487-MAX491, and MAX1487 low-power transceivers for RS-485 and RS-422 communication, each device has a drive and a receiver)
- 2012-07-10 21:28:46下载
- 积分:1