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RS485
verilog开发FPGA，实现RS485串口通信(RS485 driver for FPGA )
- 2021-02-08 06:49:54下载
- 积分：1
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信号完整性，设计FPGA的基础
信号完整性，设计FPGA的基础-signal integrity, design based FPGA
- 2022-09-25 03:05:03下载
- 积分：1
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Priority encoder in VHDL.
Priority encoder in VHDL.
- 2022-01-30 18:57:28下载
- 积分：1
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sync-and-asyn_FIFO_verilog
同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)
- 2021-03-07 14:19:29下载
- 积分：1
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scope_VGA
利用IIC接口的4路 ADC max1037，采集思路信号，通过在FPGA内部的构建DeltaSigma DAC软核，在VGA液晶显示屏上显示波形。 (IIC interface 4-way ADC max1037, collecting ideas signal the FPGA internal build DeltaSigma DAC soft-core VGA LCD display waveforms.)
- 2012-07-24 00:41:29下载
- 积分：1
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有例在VHDL
there are exemple in the vhdl
- 2022-11-14 07:15:02下载
- 积分：1
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直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为...
直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, RAM used to store look-up table, its address is 10 bits wide, the data is 8 bits wide.
- 2022-06-17 05:09:27下载
- 积分：1
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RISC(精简指令集计算机)存储程序状态机的源代码
RISC(精简指令集计算机)存储程序状态机的源代码-RISC (reduced instruction set computer) stored procedures source code of the state machine
- 2022-06-30 22:23:03下载
- 积分：1
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DDS
Verilog实现DDS线性调频，Verilog实现DDS线性调频(Verilog implementation of DDS linear FM，Verilog implementation of DDS linear FM)
- 2015-07-29 19:59:36下载
- 积分：1
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I write the digital phase
本人写的数字锁相环，有模拟数据，学习锁相环很好的材料。参考书“数字锁相环路原理与应用”编写。-I write the digital phase-locked loop, have simulated data, a good phase-locked loop learning materials. Reference book
- 2023-04-23 05:25:03下载
- 积分：1
