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Reread-machine-program
通过凌阳16位单片机实现复读机的应用的程序。(By Sunplus 16-bit MCU repeater application process.)
- 2011-07-30 16:09:07下载
- 积分：1
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Verilog digital system design tutorials, e
Verilog数字系统设计教程，作者夏宇闻电子书籍-Verilog digital system design tutorials, e-books by XIA Yu-Wen
- 2023-03-21 06:15:07下载
- 积分：1
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freq
vhdl八位十进制数字频率计的设计，顶层和数码管扫描模块(vhdl eight decimal digital frequency meter design, top-level and digital tube scanning module)
- 2012-10-09 15:09:22下载
- 积分：1
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dac5686
在FPGA上编写的通过SPI总线配置外部DAC芯片DAC5686的程序，通过板级调试，验证可用。程序通过状态机实现，将需要配置的寄存器值转为SPI总线的数据格式发送出去。 (Configure external DAC chip DAC5686 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you will need to configure the register values 椠渀琀漀 SPI bus data format sent.)
- 2014-09-11 11:05:20下载
- 积分：1
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采用systemc语言设计了一个状态机，主要包括两个进程，仿真结果表明状态机可以正常工作...
采用systemc语言设计了一个状态机，主要包括两个进程，仿真结果表明状态机可以正常工作-Systemc language designed using a state machine, mainly consists of two processes, the simulation results show that the state machine can work properly
- 2022-03-17 09:47:30下载
- 积分：1
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抢答器的VHDL语言设计 他的基本功能是，在四组参赛的情况下，首先抢答的发出抢答信号，此时其它抢答电路失去控制作用，在优先抢答的要在固定时间进行答题，否则直接扣一分
四路控制抢答器模块设计 他的基本功能是，在四组参赛的情况下，首先抢答的发出抢答信号，此时其它抢答电路失去控制作用，在优先抢答的要在固定时间进行答题，否则直接扣一分
- 2022-03-01 02:26:23下载
- 积分：1
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bt656_decode
将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)
- 2021-01-28 10:38:35下载
- 积分：1
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turbo
详细讲述TURBO码的FPGA实现原理，可作参考，不是码源(A detailed account of the FPGA implementation of principle of the TURBO code can be used as reference, not source code)
- 2012-05-01 13:12:59下载
- 积分：1
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这是一个FPGA sparttan 3E基础工程，
this a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.-this is a fpga sparttan 3e based project in which
i have made a game based on vga interface .
this file is the supporting file for keyboard interface and it also included a intro.vhdl file required for the startup animation file.
- 2022-11-15 01:50:04下载
- 积分：1
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FPGA2-DSP2-EDMA
例程是基于quartus的，FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者(Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners)
- 2020-12-04 16:09:24下载
- 积分：1
