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乘法器,实现了乘法和除法的功能,能够进行32位的运算
乘法器,实现了乘法和除法的功能,能够进行32位的运算-Multiplier to achieve the functions of multiplication and division to carry out 32-bit computing
- 2022-03-24 02:44:07下载
- 积分：1
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全数字锁相环的verilog源代码
全数字锁相环的verilog源代码-全数字锁相环的verilog源代码
- 2023-04-30 22:20:03下载
- 积分：1
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用FPGA实现数字锁相环，开发环境为ISE
用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE
- 2022-06-22 05:34:34下载
- 积分：1
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DDS_Power
FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。(FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.)
- 2007-04-17 23:43:32下载
- 积分：1
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这是8位微处理器的Verilog源代码，可以欠在Flex10k10里面
这是8位微处理器的Verilog源代码，可以欠在Flex10k10里面-This is the 8-bit microprocessor Verilog source code, can they owed in Flex10k10
- 2022-02-06 13:26:07下载
- 积分：1
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uart_byte_rx
libero soc工程，实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)
- 2020-06-21 09:20:01下载
- 积分：1
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设计一个可以小时、分钟、12小时或24小时和秒的时间…
设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。
实验平台：
1. 一台PC机；
2. MAX+PLUSII10.1。
Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report
- 2022-07-22 15:10:59下载
- 积分：1
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systolic
脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systolic）的乘法器(Pulse Multiplier: a GF (2m) domain on the Digit-Serial pulsation structure (Systolic) the multiplier)
- 2020-11-13 10:39:43下载
- 积分：1
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f_adder
该工程描述的是一位全加器，可以用此作为基础，搭建多位全加器(The project description is a full adder can use this as a basis to build a number of full adder)
- 2013-04-21 10:30:16下载
- 积分：1
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卡内基梅陇大学verilog课程讲义-unlocked
verilog讲义
卡内基梅陇大学verilog课程讲义-unlocked
卡内基梅陇大学verilog课程讲义-unlocked(Verilog Course Lectures at Carnegie Mellon, University Verilog Course Lectures at Carnegie Mellon University Verilog Course Lectures at Carnegie Mellon University)
- 2020-06-20 18:00:02下载
- 积分：1
