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多进制数字频率调制(MFSK)系统VHDL程序
多进制数字频率调制(MFSK)系统VHDL程序-Multi-band digital frequency modulation (MFSK) system VHDL procedures
- 2022-04-16 11:59:01下载
- 积分：1
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一些有用的PicoBlaze的来源。
Some useful PicoBlaze sources.
- 2022-01-26 02:08:20下载
- 积分：1
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DC-Voltmeter
Use this multimeter to make precise electronic measurements and tests. Easy-to-read LCD readout, positive set selector switch and 32" leads. AC voltage
- 2013-01-07 22:52:54下载
- 积分：1
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8路视频光端机 接收侧 VHDL源码，使用了千兆以太网SERDES芯片，基于TBI接口的PCM视频传输。...
8路视频光端机 接收侧 VHDL源码，使用了千兆以太网SERDES芯片，基于TBI接口的PCM视频传输。-8-Channel Video Optical Receiver side of VHDL source code, using the Gigabit Ethernet SERDES chip, based on the TBI interface PCM video transmission.
- 2022-12-18 19:40:04下载
- 积分：1
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traffic_lights
用Verilog实现的交通信号灯控制，主干道和支路通行的时间不相等(Using Verilog implementation of traffic signal control, the trunk road and the slip is not the same passage of time)
- 2009-03-28 18:31:31下载
- 积分：1
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FPGA 设计的四种常用思想与技巧
FPGA 设计的四种常用思想与技巧-FPGA design ideas and techniques used in four
- 2022-03-15 15:54:37下载
- 积分：1
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本例为DAC0832接口电路VHDL原代码
本例为DAC0832接口电路VHDL原代码-The DAC0832 Interface Circuit Example for VHDL source code
- 2022-08-14 02:36:10下载
- 积分：1
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基于FPGA的OFDM信号传输系统VHDL源码
基于FPGA(Field-Programmable Gate Array)的OFDM(Orthogonal Frequency Division Multiplexing)信号传输系统VHDL源码
use IEEE.std_logic_unsigned.all;
package outconverter is
constant stage : natural := 3;
constant FFTDELAY:integer:=13+2*STAGE;
constant FACTORDELAY:integer:=6;
constant OUTDELAY:integer:=9;
function counter2addr(
counter : std_logic_vector;
mask1:std_logic_vector;
mask2:std_logic_vector
) return std_logic_vector;
function outcounter2addr(counter : std_logic_vector) return std_logic_vector;
end outconverter;
package body outconverter is
function counter2addr(
counter : std_logic_vector;
mask1:std_logic_vector;
mask2:std_logic_vector
) return std_logic_vector is
variable result :std_logic_vector(counter"range);
begin
for n in mask1"range loop
if mask1(n)="1" then
result( 2*n+1 downto 2*n ):=counter( 1 downto 0 );
elsif mask2(n)="1" and n/=STAGE-1
- 2022-02-13 14:58:13下载
- 积分：1
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MifFileGen
VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子，生成的是一个定点的正弦数据表文件，需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)
- 2013-07-19 02:32:45下载
- 积分：1
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jesd204_0_ex
jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)
- 2020-11-26 14:49:31下载
- 积分：1
