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Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考....
Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.-Clock_Dithering_Verilog this is a Clock u_dither, everybody want to make Verilog-jitter can refer to.
- 2022-12-08 19:40:03下载
- 积分：1
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callback
说明： This is code of UVM CALLBACK function.
- 2020-06-24 15:40:02下载
- 积分：1
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基于DE2开发板，视频图像显示设计源代码，代码调试成功
基于DE2开发板，视频图像显示设计源代码，代码调试成功-based DE2 development board ,it is vhdl resourse code
- 2022-03-15 06:09:25下载
- 积分：1
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pj_gtx
说明： 利用高速口GTX进行快速的数据传输，包括接受和发送模块，用途广泛(The use of high-speed port GTX for fast data transmission, including receiving and sending modules, has a wide range of uses.)
- 2019-03-25 21:40:10下载
- 积分：1
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20190718 - Copy
this files describes how to build i2c block modules in verilog hdl and programming them on an fpga device
- 2020-06-21 21:20:02下载
- 积分：1
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ahbapb
说明： AMBA2.0标准的AHB2APb桥，代码通过验证(AMBA2.0 standard AHB2APb Bridge, through the verification code)
- 2008-11-30 23:57:31下载
- 积分：1
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banjian
完成一个1位全减器的设计。以全减器为元件程序完成8位减法器设计。(Completed a one minus the whole design. Full reduction is to complete eight subtraction element program design.)
- 2015-06-26 21:17:49下载
- 积分：1
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PWM
通过正弦波和三角波的比较产生SPWM波形(Through the comparison of sine wave and triangle wave produces SPWM waveform)
- 2016-12-23 14:36:56下载
- 积分：1
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sportswatch
完整的跑表设计，时，分，秒都显示，希望能对大家有用，谢啦(Complete stopwatch design, hours, minutes, seconds, show, hoping to be useful for everyone,)
- 2009-12-09 11:25:27下载
- 积分：1
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最新的ATA
最新的ATA-六总线协议源代码参考，实现DMA,PIO模式，可挂CDROM,IDE硬盘，CF卡．-the latest ATA-6 bus protocol source code reference, achieving DMA, PIO Mode, can be linked to CDROM, IDE hard drive, CF card.
- 2022-04-11 09:20:29下载
- 积分：1
