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Mult_Frequency
Based on the verilog such as frequency meter accuracy, except for measuring frequency can also measure pulse width of empty measure than 32 counts of data through the simulation SPI serial output to SCM processing and display
- 2011-07-27 10:26:29下载
- 积分：1
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Labview-Data-acquisition-card-
基于labview的数据采集系统，包括示波器和函数信号发生器，可以实现简单数据采集.(Labview-based data acquisition system, including oscilloscopes and function signal generator, can achieve a simple data acquisition.)
- 2014-01-15 21:26:04下载
- 积分：1
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该源码为VHDL语言编写的分频器，在W
该源码为VHDL语言编写的分频器，在W-4b教学平台上通过验证-The VHDL source for the prescaler languages, W-4b in the teaching platform validated
- 2022-01-24 14:12:26下载
- 积分：1
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ethernet-verilog
非常详细的千兆以太网MAC verilog代码，可以供硬件设计时有关网络的开发参考(Very detailed Gigabit Ethernet MAC verilog code, can be used for hardware design of the network to develop a reference)
- 2020-09-19 11:27:57下载
- 积分：1
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ADS8325caiyang konfgzhi
ADS8325caiyang konfgzhi
- 2023-04-14 05:15:03下载
- 积分：1
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Verilog prepared practical multi
verilog编写实用多功能电子表-Verilog prepared practical multi-function electronic Table
- 2022-04-23 06:46:24下载
- 积分：1
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StopWatch
This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
- 2013-10-04 00:53:49下载
- 积分：1
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This is is a bridge IP core to interface the Tensilica PIF bus protocol with the...
This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
- 2022-04-07 07:47:24下载
- 积分：1
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CAN协议控制器的Verilog实现
说明： 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。(FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.)
- 2020-11-26 15:29:31下载
- 积分：1
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任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。...
任意基数分频VERILOG代码，经过了编译，可以修改数字改变分频。-Arbitrary base frequency Verilog code, after compilation, the figures can be amended to change the frequency.
- 2022-08-10 12:37:41下载
- 积分：1
