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二进制除法器,采用移位相减的方法实现,位数可调
二进制除法器,采用移位相减的方法实现,位数可调-The source code of a divider
- 2023-08-14 00:00:02下载
- 积分:1
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clock_gyc_system
基于用户自定义模块的实时时钟的设计;Qsys硬件设计;(Custom real-time clock module-based design Qsys hardware design )
- 2020-12-23 09:19:08下载
- 积分:1
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设计采用Verilog HDL 16位CPU。
design cpu 16 bits by verilog HDL.
- 2022-03-11 03:09:04下载
- 积分:1
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华为经典FPGA设计全套入门技巧
华为经典设计全套入门技巧,面试经验,设计技巧(Huawei Classic Design Complete Introduction Skills, Interview Experience, Design Skills)
- 2020-07-01 23:00:02下载
- 积分:1
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RANGEN
2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码,verilog编写;包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)
- 2020-10-27 17:09:59下载
- 积分:1
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VHDL设计的功能齐全的交通灯程序,经过仿真一切功能符合要求。...
VHDL设计的功能齐全的交通灯程序,经过仿真一切功能符合要求。-VHDL
- 2022-01-25 23:26:36下载
- 积分:1
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This is a use of the VHDL language Parallel to Serial procedures, In altera deve...
这是一个用VHDL语言编写的并口转串口程序,在altera开发系统下验证通过,运用于开发板与计算机之间的通信,源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communications, can provide a reference source
- 2022-03-23 13:41:19下载
- 积分:1
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ddr3_model
一个verilog语言开发编写的简单的ddr3模型(A simple model ddr3, written with verilog language)
- 2020-08-26 17:38:13下载
- 积分:1
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P4 (3)
支持{addu、subu、lui、ori、jal、jr、lw、sw、nop}指令集的单周期CPU,verilog硬件描述语言实现(Support {addu, subu, lui, ori, jal, jr, lw, sw, nop} instruction set of one-cycle CPU, Verilog hardware description language implementation)
- 2018-12-02 17:22:40下载
- 积分:1
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eDP
eDP接口TFT-LCD显示驱动原码(verilog+c)(eDP Interface TFT-LCD display driver source code (verilog+c))
- 2020-10-17 09:17:27下载
- 积分:1